If you need help with ESD... ask me in this post

[nschutten]

Hi ESDSolutions,

I was wondering about the following: when reading about ESD, it is usually about protecting the gate of the transistor. But how about the drain/source connections (e.g. the connections of a power switching transistor)? Wouldn't the voltage at the drain/source connections go to the channel, which then (assuming the gate voltage is not affected by ESD) would result in the same effect (with only sign reversal) as when the gate would have the ESD event and the drain/source unaffected?

Many thanks in advance to anyone who can help clarify this for me!

 

[arunkumar446]

I'm new to this area, can any one give me reference to some docs which have basics discussed or tutorials on design.

Thanks in advance.

 

[skowe26]

Hi ESDSolutions

I am also doing some ESD study and have some few questions on ggnmos cell.
How is the holding voltage of ggnmos set? Is it process dependent?
What happens to the N+/PW junction after avalanche breakdown? Does it act like a zener diode?

Thanks in advance.

 

[prcken]

I'm new to this area, can any one give me reference to some docs which have basics discussed or tutorials on design.

Thanks in advance.

i recommend you to read this book
ESD in silicon integrated circuits - second edition by A. Amerasekera and C. Duvvury, 2002.

Added after 10 minutes:

Hi ESDSolutions,

I was wondering about the following: when reading about ESD, it is usually about protecting the gate of the transistor. But how about the drain/source connections (e.g. the connections of a power switching transistor)? Wouldn't the voltage at the drain/source connections go to the channel, which then (assuming the gate voltage is not affected by ESD) would result in the same effect (with only sign reversal) as when the gate would have the ESD event and the drain/source unaffected?

Many thanks in advance to anyone who can help clarify this for me!

yes, you are right. the pn jucntion can breakdown by ESD stress as well as gate oxide breakdown happens. you should keep your power down switching transistor away from connecting to the PAD directly.
usually, pn junction breakdown voltage is less than gate oxide breakdown voltage in 0.18um CMOS process technology node and above. while gate oxide is more prone to breakdown than pn junction in 100nm technology node and below.
hope this could help you.
Kehan

Added after 8 minutes:

Hi ESDSolutions

I am also doing some ESD study and have some few questions on ggnmos cell.
How is the holding voltage of ggnmos set? Is it process dependent?
What happens to the N+/PW junction after avalanche breakdown? Does it act like a zener diode?

Thanks in advance.

the holding voltage should be set above the normal operating voltage with margin in order to be latch-up immunity. yes, it's process dependent.
when the N+/PW junction after avalanche breakdown the voltage between drain to source snapbacks to the holding voltage. it's (parasitic) BJT working mechanism. i recommend you to read the MOS chapters in some of the ESD books, such as the book i mentioned above :
ESD in silicon integrated circuits - second edition by A. Amerasekera and C. Duvvury, 2002.
you will get some insights after finish the reading

 

[varunmjman]

Hey can u please explain to me whats a power cut cell and what are its uses.

 

[shashikumar.22]

hey can anybody give a link for this book

ESD in silicon integrated circuits - second edition by A. Amerasekera and C. Duvvury, 2002

Basic ESD and IO design by sanjay Dabral

 

[prcken]

Hey can u please explain to me whats a power cut cell and what are its uses.

power cut is used as conduction device between different power supllies or grounds, or between ground and ESD rail, which provides ESD current path when ESD events happend between diferent power domains.
usually, power cut is a bidirectional device for example consists of two diodes

Added after 2 minutes:

hey can anybody give a link for this book

ESD in silicon integrated circuits - second edition by A. Amerasekera and C. Duvvury, 2002

Basic ESD and IO design by sanjay Dabral

have you googled ? i think you can find it, if not, please feel free to contact me.

 

[nschutten]

Thanks, prcken, for helping me by giving some further info regarding my ESD question.

BTW: the transistor in question is not a power down transistor, it is a switching transistor for a DC/DC converter; so the source and drains need to be connected directly to the pads (no series components etc. can be used, since these only introduce losses). Since the PN junctions are very large, do you think this kind of device will be self-protecting?

 

[prcken]

Thanks, prcken, for helping me by giving some further info regarding my ESD question.

BTW: the transistor in question is not a power down transistor, it is a switching transistor for a DC/DC converter; so the source and drains need to be connected directly to the pads (no series components etc. can be used, since these only introduce losses). Since the PN junctions are very large, do you think this kind of device will be self-protecting?

hi, i've no experience in power management IC design, but i'd like to discuss with you.
i see what's your problem now, in my view, you can layout the switching transistor as ESD device, the transistor itself can withstand certain ESD stress, and you still have dedicated ESD protection device, right?
Under ESD event, your chip is not powered on, so i think you should consider the voltage protential at the gate of the switching MOS at all kinds of ESD zapping mode. for example, if the switching MOS is off, ESD current will be shunt by the dedicated ESD device. otherwise, the ESD current will flow into the switching MOS, maybe you should place a secondary ESD device at the other end of the switching MOS in order to provide an ESD current path.
that's my opinion.

 

[jiafulin]

dear ESD solution
how can I generate esd signal in ADS ,thx

 

[laststep]

Hi ESDSolution,

I encounter and ESD device 'GGnMOS structure" which using
another nmos to form the ground connection at the gate side. May I know what is the diff and advantage by using this soft ground instead of the firm/real ground conncetion?

 

[pbs681]

hi all,

have a basic question here. I am studying one IO pad design, NMOS and PMOS driver is used as an ESD device. But, I don't know why only NMOS driver has ballast resistor (nwell res). Why PMOS driver doesnt have it. Appreciate ur help!

 

[holddreams]

Hi,

If PMOS driver uses ballast resistor, how to realize? With pwell res?
If there is no Pwell for the process, how should we do?

hi all,

have a basic question here. I am studying one IO pad design, NMOS and PMOS driver is used as an ESD device. But, I don't know why only NMOS driver has ballast resistor (nwell res). Why PMOS driver doesnt have it. Appreciate ur help!

 

[jardila]

Hi,

I'm an undergraduate student and I'm working in my thesis about esd protection circuits. I had some problems of convergence with simulations. I'm using hspice.
what is the apropiate netlist of the nmos transistor to simulated esd circuits? I readed papers about simulations and the convergence problem, but I try and I can not find solution.


Best Regards.

 

[prcken]

dear ESD solution
how can I generate esd signal in ADS ,thx

i think if you want to model HBM, just build RLC HBM network the same as in spectre or hspice.

 

[visrimhal]

Hello guys, not sure if the thread is active, but I have a question regarding spark gaps.
If a discharge can be grounded using a spark gap, is it not possible that stray discharges jump from the ground tip of the spark gap on to the signal end?!
Any such experiences?

 

[amnakhan786]

plz its urgent about esd

dear esd solns,
i am working on energy meter project which contains ade7758 evaluation board.this board allows 220v lines to be interfaced directly thru attenuation networks which reduce voltage 1000 times.the input pins can bear overvoltage upto 6v without risk of permanent damage.i want to inquire that if my board is powered off and on its input port pins i apply220v rms directly then an open volage will appear across the board.can my circuit bear that voltage provided that the input pins have internal esd protection.if i power on the board and then connect 220v line a spark will be created which i want to avoid.can esd protection circuitry route away such voltage fromsensitive circuitry.
another qs is when in power off stage we are not providing any voltage and ground there is no higher and lower potentials then how does any component workhow does esd circuitry work.
.i need the answer in 24 hrs.it very urgent.

 

[jardila]

Hi,

I must design a power rail supply clamp. I have many options: RC-with 3-inverters, RC- thyristor-delay,
SRAM-based. How can I choose the best?

Best Regards,

 

[xiangxianga396]

Dear ESD solution,

Would you please tell me the difference of using ESD P/N diode or ESD P/N MOS for I/O protection in 0.13um process; I would like to know why some one use ESD P/N diode, some use ESD P/N MOS, thanks a lot!

 

[mycelldevice]

Hi:
I meet a big problem, I use rc LDNMOS for 40v I/O esd protection, they are falled all. r=0.7K, c=2pF, LDNMOS w=50u l=1.2u m=30, vth=0.9v
anybody can help help help me......