if you have USB2.0 OTG IC design experience at China

Similar threads

• Error: [127205403]: CMPPF_010: A design must contain at least one net.

  • Started by billdro
  • Jun 20, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• X

  Still have problem with understanding `include in Verilog

  • Started by Xenon02
  • Oct 2, 2023
  • Replies: 8

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  How can I run verilog code with data at a specific time in the past?

  • Started by alexis57
  • Jan 28, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• P

  Generic error at Vivado Simulator, how to debug this?

  • Started by pbernardi
  • May 20, 2023
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• X

  How do I interpret "if" statement in different always_comb situations ?

  • Started by Xenon02
  • Jan 6, 2023
  • Replies: 38

  PLD, SPLD, GAL, CPLD, FPGA Design