If I connect CMOS CML cells do I have to use level shift?

[Puppet1]

Logic in CMOS

I have asked repeatedly here about CMOS Current Mode Logic but no dice.

So here is a question:

If I connect CMOS CML cells together, let's say a MUX to a flip flop for retiming, do I HAVE to use a level shift ?

Or do I size the transistors, such the input and output bias points are the same.

Please advise.

 

[goodboy_pl]

Re: Logic in CMOS

There is no need to level shifter!
to design a latch use the following steps:
1. set the tail current source to a predefined value (for example 100 uA)
2. load resistors at drain=~0.8V/100uA
3. set the cross coupled transistor W/L ratio such that Gm.R>1
4. use the same W/L for diff. pair at the input!
5. use 2*W/L of above for clock transistors!

NOTE: it is assumed that the latch must drive a block like itself!

after all steps your latch will work, but optimization is necessary to provide better performance and speed.

for higher speed, use a larger current for the tail.

the design of other blocks like gates and MUX more or less the same!

BEST!