Identifier "signed" is not directly visible

[kalyansrinivas]

Dear friends

The libraries i added to my VHDL file are

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

When i start compiling my design I get the issue

Identifier "signed" is not directly visible

I have read many reviews but i whatever i read says not to include too many libraries

i added only the above libraries

But Still i face this issue

My compiler is Model sim

Regards
M Kalyan srinivas

 

[lucbra]

could you elaborate a little further and post some code?

I assume you have declared a port or signal with a reserved word (in this case signed).

 

[TrickyDicky]

the problem is probably because you have included std_logic_arith in the same code. If you include std_logic_arith and numeric_std, then because they both declare the types signed and unsigned, you cannot see either without specifying which one you want:

eg.
signal a : numeric_std.signed(7 downto 0);
signal b : std_logic_arith.signed(7 downto 0);

now, because they are not the same type, then this is is illegal:

a <= b;

you would have to write:

a <= numeric_std.signed(b);

So, the best thing to do is delete std_logic_arith (as it is a non-standard library)

 

[kalyansrinivas]

firstly thanks for your replies

The libraries included are just

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

I used the following statement inside my architecture

process(clk)
begin
if rising_edge(clk) then
sum <= sum + std_logic_vector(resize(signed(data(25 downto 0)),40));
end if;
end process;

when i included the following library ieee.std_logic_signed.all;

The issue is resolved and i got the results but i think this library is non standard

so please tell me whether i am going in the correct way

Regards
M Kalyansrinivas

 

[TrickyDicky]

no, you are not correct, because std_logic_signed is not a standard library. you should not be adding std_logic_vectors together.

 

[FvM]

Identifier "signed" is not directly visible

I fear, the initial post is incorrect somehow. The said error can be expected when importing std_logic_signed without std_logic_arith. But not with the library configuration reported in the initial post. Because signed is visible in IEEE.NUMERIC_STD.

Whatsoever, the thread is showing once more why we should inist on complete code examples including libraries, interface and signal definitions.

 

[kalyansrinivas]

firstly thanks for your time

Herewith i paste my code,
Initially when i started the discussion i said that "Identifier "signed" is not directly visible"

for that i made a change in my code instead of using signed to convert a std_logic_vector i used to_signed to convert

you can see in the below code near the resize operator

Now i am facing with issue " No feasible entries for infix operator "+"


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
port (
clock : in std_logic;
reset : in std_logic;

adc_sample : in std_logic_vector (11 downto 0);
isum_out : out std_logic_vector(39 downto 0);
qsum_out : out std_logic_vector(39 downto 0)
);
end test;

architecture Behavioral of test is

signal fa_i,conj_fa_i : std_logic_vector(11 downto 0);

signal isum_128,qsum_128 : std_logic_vector(39 downto 0);

begin

fa_i <= adc_sample; conj_fa_i <= not(adc_sample)+'1';

--12 bit width will be resized to 40 bits

process(clock)
begin
if rising_edge(clock) then
isum_128 <= isum_128 + std_logic_vector(resize(to_signed(fa_i(11 downto 0)),40));
qsum_128 <= qsum_128 + std_logic_vector(resize(to_signed(conj_fa_i(11 downto 0)),40));
end if;
end process;

isum_out <= isum_128;
qsum_out <= qsum_128;

end Behavioral;

 

[FvM]

You can't add std_logic_vector, as previously stated.

 

[TrickyDicky]

you need to add signed types, not std_logic_vector.

 

[kalyansrinivas]

thanks for the reply

As you mentioned i have to do arithmetic operations only on signed or unsigned data types

now my problem is the input is coming from a fifo which is of type std_logic_vector and now i would like to convert it to signed data type

I searched and not able to find a type conversion for std_logic_vector to signed in numeric_std library

My intention was to convert the std_logic_vector only before the arithmetic operation and later to change it to std_logic_vector

Also Can you please tell me with reference to my previous code how can i code

conj_fa_i <= not(adc_sample)+'1'; in signed format i mean should we change '1' also signed



Thanks & regards
M Kalyan srinivas

 

[TrickyDicky]

Because signed and std_logic_vector are similar types, a standard type conversion is possible:

signal my_signed : signed(7 downto 0);
signal my_slv : std_logic_vector(7 downto 0);

my_signed <= signed( my_slv )

 

[kalyansrinivas]

Hi tricky dicky

how to code a twos complement form

For example can i do like this

conj_fa_i : signed(7 downto 0);
adc_sample : std_logic_vector(7 downto 0);l

conj_fa_i <= signed(not(adc_sample)) + unsigned('1'); two's complement as '1' is a std_logic format

Thanks & regards
M Kalyansrinivas

 

[TrickyDicky]

first of all, a std_logic_vector is not a signed. so you either need to declare conj_fa_i as signed or convert the result to a std_logic_vector.

keeping with your signal declarations, you can do this:

conj_fa_i <= std_logic_vector( (not signed(adc_sample) ) + 1);