I would like to know how the hardware part of I2C is implemented. I mean, consider data register is a buffer and each bits will be left shifted and transmitted in the SDA (with open drain logic). Similarly what kind of logic are behind the status registers and what are the gates, transistor or buffers are available.
hai bigdogguru.. actually i am not trying to implement softI2C or bit banging type coding. I wanted to know the functionality of I2C hardware.
For example
1. a port pin of micro controller has a latch, one or 2 FET.
2. a serial buffer is having shift registers and transmits the data bit by bit.
Similarly, a I2C hardware constructed by what elements and how it is finding the status of the bus. I didnt find documents related to this details
The first two link shows only about the software implementation. The hardware part is not available except open drain configuration. I think the status registers or clock configuration circuits to be presented to understand complete functionality. I am not going to do any research but i feel knowing these details will be good.
Sorry i know very little about FPGA's.. Anyway i have registered to download the design. it may take 2 or 3 days. Mean while i would like to know any other details related to my topic.