It helps you do an efficient layout that optimizes both area and power as well as saving time. You get an initial estimate of the chip area and the relative positions of the clocks with respect to each other. You can determine how the blocks will be connected, what buses are needed, where the signals will enter the block (from the right side, left side..etc). It also restricts the area and aspect ratio of each block so that each design can have a well-defined area/interface