I want divide clk by five . sir.
I found a logic circuit by googling. sir.
so i apply that logic circuit to verilog code, but it derive wrong result(not what i want).
could you give me a hint for me sir?
Hi,
usual click dividers can divide /(2 × n) only.
* Divide by 5 may be generated by counting to 2 then 3, but gives 40%/60% duty cycle.
* One way to getv50%duty cycle is to use combinatoric logic
* Or to use both clock edges
Earlier I wrote some behavioral code for the schematic with the yellow background and ran a simulation on it to verify the schematic was correctly implementing a divide by 5.
Like I already stated, the inversions on the gates is missing in the OPs implementation, without those inversions the circuit does not work. If the circuit is correctly implemented with the inversions on the gate inputs the circuit does work as a divide by 5. Although I don't think the multiple gate driven output is a good way to generate the divide by 5 output clock (it's pretty much a given the clock won't have a 50% duty cycle due to path delay variations).
Nope it's not a Verilog race condition problem. The Z output is due to the "latch" structure in the output gates, it never gets initialized, because of the problem I noticed in the OPs implementation.
Hi,
usual click dividers can divide /(2 × n) only.
* Divide by 5 may be generated by counting to 2 then 3, but gives 40%/60% duty cycle.
* One way to getv50%duty cycle is to use combinatoric logic
* Or to use both clock edges
Klaus
The existing schematic they tried to implement has combinational logic (along with a latch) to generate the clock output. I thought of a way to modify the circuit to use both clock edges, but that only gives you a 50% duty cycle if the input clock has a 50% duty cycle. Most clocks don't have 50% duty cycle unless they are divided down from a 2*n clock source.