# I want divide clk by five. could you please give me an hint for me?

#### hyunwoo

##### Newbie
I want divide clk by five . sir.
I found a logic circuit by googling. sir.
so i apply that logic circuit to verilog code, but it derive wrong result(not what i want).
could you give me a hint for me sir?

Code Verilog - [expand]1
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module clk_div_five(clkby5,
clk);
inout clkby5;
input clk;
wire a,b,c,d,e,f,g;

and_gate_3in and_3(a,b,c,//input
d);
dff dff1(clk,d,a);
and and1(e,c,a);
dff dff2(clk,e,b);
dff dff3(clk,b,c);
or or1(f,clkby5,a);
or or2(g,clk,b);
and and2(clkby5,f,g);
endmodule

Code Verilog - [expand]1
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module  and_gate_3in( input_a,input_b,input_c,//3input and gate
output_y);
//INPUTS
input   input_a;
input   input_b;
input   input_c;
//OUTPUT
output output_y;

//Declaration of 3 input AND Gate

assign output_y = (input_a) & (input_b) & (input_c);

endmodule

Code Verilog - [expand]1
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module dff(clock,reset,q);// d flip flop
input clock,reset;
output q;
reg temp;
always @(posedge clock or negedge reset)
begin
if (!reset)
begin
temp<=0;
end
else
begin
temp<=~temp;
end
end
assign q=temp;

Last edited by a moderator:

##### Super Moderator
Staff member
You are missing a bunch of inversions on inputs to the gates, so don't expect the circuit to work as it was meant to.

#### dick_freebird

##### Advanced Member level 5
There is also a lack of any delay in the gates
or FFs as far as I can see. So there could be
built in race conditions that verilog can't
resolve.

#### Akanimo

##### Advanced Member level 2
Just feed the clock into a modulo-5 counter. The output (MSB) will be a divide-by-5 version of the clock.

#### KlausST

##### Super Moderator
Staff member
Hi,
usual click dividers can divide /(2 × n) only.
* Divide by 5 may be generated by counting to 2 then 3, but gives 40%/60% duty cycle.
* One way to getv50%duty cycle is to use combinatoric logic
* Or to use both clock edges

Klaus

##### Super Moderator
Staff member
Earlier I wrote some behavioral code for the schematic with the yellow background and ran a simulation on it to verify the schematic was correctly implementing a divide by 5.

Like I already stated, the inversions on the gates is missing in the OPs implementation, without those inversions the circuit does not work. If the circuit is correctly implemented with the inversions on the gate inputs the circuit does work as a divide by 5. Although I don't think the multiple gate driven output is a good way to generate the divide by 5 output clock (it's pretty much a given the clock won't have a 50% duty cycle due to path delay variations).

There is also a lack of any delay in the gates
or FFs as far as I can see. So there could be
built in race conditions that verilog can't
resolve.
Nope it's not a Verilog race condition problem. The Z output is due to the "latch" structure in the output gates, it never gets initialized, because of the problem I noticed in the OPs implementation.

Just feed the clock into a modulo-5 counter. The output (MSB) will be a divide-by-5 version of the clock.
As Klaus points out this won't give you a 50% duty cycle clock.

Hi,
usual click dividers can divide /(2 × n) only.
* Divide by 5 may be generated by counting to 2 then 3, but gives 40%/60% duty cycle.
* One way to getv50%duty cycle is to use combinatoric logic
* Or to use both clock edges
Klaus
The existing schematic they tried to implement has combinational logic (along with a latch) to generate the clock output. I thought of a way to modify the circuit to use both clock edges, but that only gives you a 50% duty cycle if the input clock has a 50% duty cycle. Most clocks don't have 50% duty cycle unless they are divided down from a 2*n clock source.

hyunwoo

### hyunwoo

points: 2
so kind doctor octopus

#### hyunwoo

##### Newbie
Just feed the clock into a modulo-5 counter. The output (MSB) will be a divide-by-5 version of the clock.
I need to use D-flipflop for make div_5 frequency. thanks for your counsel!~^^~!