hyunwoo
Newbie
I want divide clk by five . sir.
I found a logic circuit by googling. sir.
so i apply that logic circuit to verilog code, but it derive wrong result(not what i want).
could you give me a hint for me sir?
I found a logic circuit by googling. sir.
so i apply that logic circuit to verilog code, but it derive wrong result(not what i want).
could you give me a hint for me sir?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module clk_div_five(clkby5, clk); inout clkby5; input clk; wire a,b,c,d,e,f,g; and_gate_3in and_3(a,b,c,//input d); dff dff1(clk,d,a); and and1(e,c,a); dff dff2(clk,e,b); dff dff3(clk,b,c); or or1(f,clkby5,a); or or2(g,clk,b); and and2(clkby5,f,g); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module and_gate_3in( input_a,input_b,input_c,//3input and gate output_y); //INPUTS input input_a; input input_b; input input_c; //OUTPUT output output_y; //Declaration of 3 input AND Gate assign output_y = (input_a) & (input_b) & (input_c); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module dff(clock,reset,q);// d flip flop input clock,reset; output q; reg temp; always @(posedge clock or negedge reset) begin if (!reset) begin temp<=0; end else begin temp<=~temp; end end assign q=temp;
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