jarodz said:Is the synchronous reset FF that you mean FF without reset pin?
As I know, synchronous reset FF is consisted of a FF without reset pin and a mux.
Therefore the area of synch reset FF is larger than async reset FF.
In a design, some of FFs can be without reset.
Regards,
Jarod
sandusty said:For the DFT issues, please keep the async. reset for all the flops. However, you would like to use sync ckts at the very input point to re-sync the async. reset-singal from another chip.
Currently the scan-insertion tools can fix the sync reset problem by gating the reset signal generated in the chip. But for the safity reason, we would like to keep all the flops reset in the async method.
jarodz said:Is the synchronous reset FF that you mean FF without reset pin?
As I know, synchronous reset FF is consisted of a FF without reset pin and a mux.
Therefore the area of synch reset FF is larger than async reset FF.
sunms said:I used asynchronous reset in my design, and now found in the test that the chip doesn't work stable.
Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.
But now in the system test,there's need that I have to reset the datastream connecting to another chip. And the chip's output will be in chaos.
So can anyone tell me how to avoid this in the future design. Only refer to synchronous reset is also not a good way,for it will include many additionl logics.
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