sunms
Junior Member level 3
I used asynchronous reset in my design, and now found in the test that the chip doesn't work stable.
Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.
But now in the system test,there's need that I have to reset the datastream connecting to another chip. And the chip's output will be in chaos.
So can anyone tell me how to avoid this in the future design. Only refer to synchronous reset is also not a good way,for it will include many additionl logics.
Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.
But now in the system test,there's need that I have to reset the datastream connecting to another chip. And the chip's output will be in chaos.
So can anyone tell me how to avoid this in the future design. Only refer to synchronous reset is also not a good way,for it will include many additionl logics.