Kynix
Banned
Hello~everyone
I’m a beginner in the FPGA. The past days I have learned the language of Verilog HDL and digital circuit. I have changed the following code and I am get into hot water. The conclusion is about the usage of Parameter and assign. In the process of learning Verilog,I haven’t seen the usage of some keywords while they are just understood by some examples. As a result, the problems come up when using. Anybody can teach me ? I will resign myself to your guidance.
Your help will be appreciated!Thanks a lot.
I’m a beginner in the FPGA. The past days I have learned the language of Verilog HDL and digital circuit. I have changed the following code and I am get into hot water. The conclusion is about the usage of Parameter and assign. In the process of learning Verilog,I haven’t seen the usage of some keywords while they are just understood by some examples. As a result, the problems come up when using. Anybody can teach me ? I will resign myself to your guidance.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 module test_Change1 (A, B, C, L); input A, B, C; output L; reg a = 1'b1, b = 1'b1, c = 1'b1; //assign a = 1'b1; //assign b = 1'b1; //assign c = 1'b1; //parameter a, b, c; always @(posedge A) * * * * a = 1'b0; always @(posedge B) * * * * b = 1'b0; always @(posedge C) * * * * c = 1'b0; assign L = (a&b)|(a&c)|(b&c); endmodule
Your help will be appreciated!Thanks a lot.
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