- a 2-bit counter that counts 2, 1, 0, 2, 1, 0 … (If the counter happens to be in state 3 in the beginning, it must first go to zero: 3, 0, 2, 1, 0, 2, 1, 0 …)
- a 3-bit counter that counts 7, 5, 1, 0, 7, 5, 1, 0 … (If the counter happens to be in state 2, 3, 4 or 6 in the beginning, it must first go to zero, e.g.: 2, 0, 7, 5, 1, 0, 7, 5, 1, 0 …)
if you copy and paste that code into any of the verilog program it will synthesis to a graphical diagram. Or you can just draw state-diagram with bits and logically performs on the state-bit for transitions.