czarek92
Newbie level 1
I made a program, code taken from the book FPGA: author Pong. The program applies to machines FSM. Help, I do testbench and supplement it, because as I create automated test wprogramie that I need to add something :/
Please!!
Code:
`timescale 1ns / 1ps
module edge_detect_gate
(
input wire clk, reset,
input wire level,
output wire tick
);
//signal declaration
reg delay_reg;
//delay register
always @(posedge clk, posedge reset)
if (reset)
delay_reg <= 1'b0;
else
delay_reg <= level;
//decoding logic
assign tick = ~delay_reg & level;
endmodulePlease!!