I need test bench in Verilog

[czarek92]

I made ​​a program, code taken from the book FPGA: author Pong. The program applies to machines FSM. Help, I do testbench and supplement it, because as I create automated test wprogramie that I need to add something :/

`timescale 1ns / 1ps
module edge_detect_gate
	(
		input wire clk, reset,
		input wire level,
		output wire tick
    );
	 
	 //signal declaration
	 reg delay_reg;
	 
	 //delay register
		always @(posedge clk, posedge reset)
			if (reset)
				delay_reg <= 1'b0;
			else
				delay_reg <= level;
		
	//decoding logic
	assign tick = ~delay_reg & level;


endmodule

Please!!

 

[ads-ee]

I can't even tell what you are asking help on: help in fixing a testbench, help in how to add something to a testbench? As you haven't posted any testbench code we can't help you fix anything.

If you are asking us to write the testbench, don't bother. I doubt you'll find anyone who is willing to do your work for you. Sorry, but your post makes you appear lazy.

 

[mrflibble]

If you're not sure how to write testbenches, this is a decent start: https://www.asic-world.com/verilog/art_testbench_writing.html