I have a strange situations with Spartan FPGA

[hallovipin]

friends,
I am trying to interface AD9224 40 MSPS ADC to spartan 3 FPGA. I am generating 12.5 Mhz clock with FPGA and giving it to ADC as a sampling clock.
What I observe that when I am feeding clock to ADC analog signal (which is to be sampled) attached to it gets very noisy.
I went for analysis and found that the noise frequency is exactly that of ADC clock frequency. I had separate analog and digital ground which are shortedonly at the supply input.
any comment

 

[permute]

Firstly, high end ADCs benefit from not letting the FPGA touch the clock. Things like DCMs can add a relatively huge amount of jitter.

the S/H of the ADC can draw small bursts of current from the input. Its possible that the input has an excessively high impedance. In such cases, the normally small currents at the input can appear as a large noise source.

 

[Malek Lamari]

please explain more your situation.
are you trying to sample a 12,5 MHz with an ADC working at 12,5 ?
in this case, you have to feed the ADC with a clock signal 2 times greater than the input (to be sampled) or more as told by Nyquist law Fs>2*F.
but in practice, it is recommended to get a clock signal greater than 5 times the frequency of the input.
good luck.

 

[permute]

Fs >= 2*B. There is no requirement that a lowpass filter is used for anti-aliasing -- a bandpass filter is also acceptable if the analog input bandwidth is high enough.

This is likely unrelated to the OP's problem of the clock being injected back onto the physical analog input. After all, it takes a bit of effort to measure noise at Fs using the same ADC!

 

[FvM]

Sampling ADC should be generally operated with an input buffer amplifier or a low impedance source. Otherwise, you should have at least RC filters that drain off part of the sampling signal coupled to the input pins. For best noise supression, use differential input signals to the ADC.

Regarding analog and digital grounds, the datasheet requires:

The AVSS and DRVSS pins must be joined together directly under the AD9224.

An additional remark about ADC clock jitter. Permute's comment is important for those applications, where clock jitter directly turns into signal-to-noise ratio degradation, e.g. digital receivers. If you're only interested in the time domain representation of input signals, e.g. pulse parameters, the additional jitter introduced by the FPGA clock tree can be tolerable.

 

[hallovipin]

Thanx to all for your valuable suggestions.
My signal frequency is 40 kHz while sampling clock to the ADC is 12.5mHz.

I examined the FPGA clock not much of jitter is there. I totally suspect the analog and digital ground layout pattern. As mentioned by Fvm both have to be shorted directly under the ADC. I had them shorted at supply input. But can this cause such a serious problem. Later I put even a jumper to short both the grounds as near the ADC as possible but that too didnt help.
One more thing I observed that even the supply for ADC is not switched ON..if I simply feed clock to ADC without having supply on..analog input gets noisy. I am using 50 ohm resisters in series with ADC analog input.

Plz help..

 

[FvM]

I examined the FPGA clock not much of jitter is there.

Well, it's not simple to observe at those low levels that matters for some applications. With 40 kHz signal frequency, you can ignore it, however.

if I simply feed clock to ADC without having supply on..analog input gets noisy.

Shouldn't be done according to maximum ratings specification. If the clock source is current limited, it hopefully cause no harm.

Besides the discussed problem of analog input charge injection by the sampling unit, the circuit layout, particularly grounding and supply bypassing may be a problem.

If your input signal is rather low frequency, you can have "huge" RC filters at the ADC input without threatening the frequency response.

 

[hallovipin]

Finally I figured out the problem.
It was a grounding issue. Though ADC has two separate grounds (AGND and DGND) they should be shorted as close to ADC as possible and the most important thing is that these both grounds should not be much far from system ground i.e. to keep ground impedance as less as possible.

 

[bhoomi_shah2906]

Finally I figured out the problem.
It was a grounding issue. Though ADC has two separate grounds (AGND and DGND) they should be shorted as close to ADC as possible and the most important thing is that these both grounds should not be much far from system ground i.e. to keep ground impedance as less as possible.

Hey Hallovinpin,


I am facing the same problem as u were.. i have connected the grounds as close as possible. but still the problem has not been solved.. I want to know your circuit that at the input of ADC what you have used??

Had You used any ADC driver IC or Op-amp ?? which type of input you have given single ended or differential??

Please help me.. its really important for me to get the output. I have input signal of 10khz-20khz frequency and sampling frequency of 10Mhz.. This frequency has been generated by FPGA. Also let me know that have you used any buffer from FPGA to ADC clock pin???