I have a problem in creating a signal in vhdl counters

k.vasu babu said:

i have a problem in creating a signal in vhdl counters

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a signal should be counted b/w 0 to 32 & after 32 it should b all ones & again when it sees 0 it should be counted

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ranjana.foru said:

SIGNAL count: std_logic_vector(5 downto 0);
begin
process(clk,reset,count)
begin
if reset='0' then
count<="000000";
else
if clk'event and clk='0' then
if count<"100000" then
count<=count+1;
elsif count ="100000" then
count<="111111";
else
if count="111111" then
count<="000000";
end if;
end if;
end if;
end process;

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SIGNAL count: integer range 0 to 63;
begin

process(clk,reset)
begin
	if reset='1' then   --it makes more sense use active high reset internally. It doesnt use any more current
		count <= 0;
		
  elsif rising_edge(clk) then
		if count < 32 then
			count<=count+1;
			
	  elsif count = 32 then
			count <= 63;
			
		elsif count=63 then
			count <= 0;
			
		end if;
	end if;
end process;