I have a problem in creating a signal in vhdl counters

[k.vasu babu]

counters

i have a problem in creating a signal in vhdl counters
a signal should be counted b/w 0 to 32 & after 32 it should b all ones & again when it sees 0 it should be counted

 

[amraldo]

Did you try writing any code?
--
Amr

 

[cvc]

Re: counters

i have a problem in creating a signal in vhdl counters

What is the "problem"? Compile error? Simulation issue?

a signal should be counted b/w 0 to 32 & after 32 it should b all ones & again when it sees 0 it should be counted

That looks like your requirement - where is your attempt to solve it?

TeamCVC
www.cvcblr.com/blog

 

[mpatel]

Problem will come only after you start to write the code

 

[lmtg]

If or when would be useful,

 

[permute]

I'm sorry, can someone restate the problem in a way that makes sense? so far it sound like the OP wants something that counts: 0, 1, 2, ... 31, 32, 63, 63, 0

 

[ranjana.foru]

SIGNAL count: std_logic_vector(5 downto 0);
begin
process(clk,reset,count)
begin
if reset='0' then
count<="000000";
else
if clk'event and clk='0' then
if count<"100000" then
count<=count+1;
elsif count ="100000" then
count<="111111";
else
if count="111111" then
count<="000000";
end if;
end if;
end if;
end process;

count is counting every 0 of clk and this strts from 0 to 31 then on 32 it give all one ,and then repeat .
change it accordingly
this is as per the information u provide,let me know if ny further issue

 

[TrickyDicky]

SIGNAL count: std_logic_vector(5 downto 0);
begin
process(clk,reset,count)
begin
if reset='0' then
count<="000000";
else
if clk'event and clk='0' then
if count<"100000" then
count<=count+1;
elsif count ="100000" then
count<="111111";
else
if count="111111" then
count<="000000";
end if;
end if;
end if;
end process;

Why not use integers, and make your code much much easier to read?

you can then also avoid using std_logic_vectors for anything arithmetic - a std_logic_vector is not a number, it is a collection of bits. It is not intended for anything other than being a load of bits. This is why VHDL has the typing it does.

when I see

if some_slv < "100000" then

I have no idea if "100000" represents 32 or -32 without looking at what packages you have used. If it was -32 it would always fail. If you use types for what they are meant for, you can be clear with what you write:

if my_cnt < 32 then

SOOOO much clearer code.

You also have count in the sensitivity list when it shouldnt be.

So lets imrpove on reability:

SIGNAL count: integer range 0 to 63;
begin

process(clk,reset)
begin
	if reset='1' then   --it makes more sense use active high reset internally. It doesnt use any more current
		count <= 0;
		
  elsif rising_edge(clk) then
		if count < 32 then
			count<=count+1;
			
	  elsif count = 32 then
			count <= 63;
			
		elsif count=63 then
			count <= 0;
			
		end if;
	end if;
end process;

 

[permute]

Its all preference.

I don't generally like the < operator, but I'm sure the tools would do the right thing. in this case, you could have:
if 32 count = 1's
else count++
and then appropriate comments.

as if count is less than 32, it should inc. if count is 63, increment will also move to 0. 33-62 are undefined, but its probably better to increment.

if you also subscribe to the use of sync resets, it also gives the benefit that the built-in reset pin can be used for logic.

I generally don't use integers. Too often I have big int values, like 48-96b, or 32b unsigned ints.

 

[ranjana.foru]

in querry k.vasu mentioned that after 32 all bits turn to 1 ,thats why i took it in bits ,else it culd b integer as well ,unsigned library need to b added n as i m initializing d count on reset and it start with 0. i hpe there is no other problm.