Hi,
I wrote a piece of code to test signed calculation. The code doesn't work as what I expected, I can't find the souce of bug. Can anybody give me some help? thanks.
I assign sign_a to -1. Since -1<0, I expect result_a would be assigned to 0. but after simulation, the result_a is assigned to -1, which confused. Can anybody give me some guide? thnaks.
Suggest to read Verilog LRM "11.3.3 Using integer literals in expressions" and "11.8 Expression evaluation rules" to understand how your code is read by the compiler.
I guess that the literals with base specifiers are causing more confusion than being helpful.
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Looking at some details
LRM 11.4.4 Relational operators (...) When one or both operands of a relational expression are unsigned, the expression shall be interpreted as a comparison between unsigned values.
signed [8:0] has a range of -256 to 255, respectively 0 to 511 if interpreted as unsigned value, the comparison (sign_a > 511) is always false and makes no sense either.
Because (sign_a < 10'd0) is performed as unsigned comparison it's false for all negative values. Try (sign_a < 9'sd0) or simply (sign_a < 'sd0) to enforce a signed comparison.
Hi FvM,
I have read your post and have one question: sign_a has a range of -256 to 255. This sign_a compares with 10'd511, so both of the operands are unsigned, this means sign_a will be 0x3ff, which is unsigned 1023, it is larger than 10'd511, so the result_a should be 10'd511, right? but simulation result_a isn't that. Could you please help me to find what I missed again? thanks