I am confused about the Negative time in STA

[echoas]

Now, I'm reading the book"STA for Nanometer Design". In Chp3 about the setup and holdtime check.
The Original sentences in this book in page 64:
Notice that some of the hold values in the example above are negative. This is acceptable and normally happens when the path from the pin of the flip-flop to the internal latch point for the data is longer than the corresponding path for the clock. Thus, a negative hold check implies that the data pin of the flip-flop can change ahead of the clock pin and still meet the hold time
check.

Now, I'm confused about the above sentence. It said that the data path is longer than the clock. why ahead? I think it produced by the delay of clock resulting in ahead.

anyone can explain it in details?
regards!

 

[kripacharya]

The key word is Hold-time. It's not Setup-time. Hold time is the period AFTER the clock edge during which data must not be changed.

Now if the data path is longer, hence even though at the external pin the data may change before the clock edge, internally the data will continue to be valid for some time at the latch point. Get it ?

Your confusion & concern would be valid if this was for Setup-time !!

 

[echoas]

The key word is Hold-time. It's not Setup-time. Hold time is the period AFTER the clock edge during which data must not be changed.

Now if the data path is longer, hence even though at the external pin the data may change before the clock edge, internally the data will continue to be valid for some time at the latch point. Get it ?

Your confusion & concern would be valid if this was for Setup-time !!

kripacharya：
Thank you for your explanation. I know what is setup time and hold time. I just don't know why the path delay must longer than the clk in negative hold time case. I make a misunderstanding about the reference timing at the "begining" of timing "ZERO"......

The correct understanding is that " All the timing is referenced to the nets entering the device". Then the above sentence is correct.

 

[kripacharya]

... " All the timing is referenced to the nets entering the device".....

I would have thought that's obvious ?

 

[echoas]

I would have thought that's obvious ?

Now i have a new recognition on timing. I'm a beginner at STA, having many questions about timng. Thank you for your answer helping me correct the misunderstanding in timng.

regards!

 

[kripacharya]

No no don't get me wrong !! I'm no expert in STA, but for all timing, there has to be some reference point.
In fact for any measurement there has to be some reference point.