Hwo to design PLL process.

[option318]

pll process simulation

Hi, i want to design PLL system.but hwo to design process？
some "Kvco gain"."Kpfd gain"."Phase margin"."Gain margin" or else.
can you tell me. thanks.

 

[pfd001]

hwo to design charge pump for pll

you'd better set up a behavioral model for the PLL. It will help you understand the system. and you can get the spec of Kvco, phase margin from that.

 

[pfd001]

you'd better set up a behavioral model for the PLL. It will help you understand the system. and you can get the spec of Kvco, phase margin from that.

 

[marylin]

are the behavioral model the same?

if not ,why?

 

[northeast1]

Hi, i want to design PLL system.but hwo to design process？
some "Kvco gain"."Kpfd gain"."Phase margin"."Gain margin" or else.
can you tell me. thanks.

1. Design the VCO to determine the Kvco.
2. Matlab behavior simulation for open loop and close loop simulation to determine
charge pump current and C1 C2 R
3. Design PFD Charge pump Counter and so on according to your matlab
parameters
4. SPICE simulation.

 

[jecyhale]

Hi, i want to design PLL system.but hwo to design process？
some "Kvco gain"."Kpfd gain"."Phase margin"."Gain margin" or else.
can you tell me. thanks.

Firstly, design a VCO and confirm it SPEC including Kvco, center frequency, and tuning range and corrent.
Secondly, confirm the reference frequency used in PLL, then design PFD and CP.
Thirdly, design a suitalbe loop filter. which inlcude phase margin, and bandwidth and lock time etc.