HV problem in AMIS 0.35um technology.

[iVenky]

In AMIS 0.35 um technology if I include the HV PMOS and simulate it in Cadence Virtuoso, I get this error in the log "PMOS can have only three terminals as opposed to four teminals" (or something of that sort). But actually PMOS has four terminals - source,drain,gate,bulk. There is no problem with the HV NMOS (In HV NMOS bulk and source are connected together by default which is strange by the way ). Can anyone help me with this?

Thanks

 

[erikl]

(In HV NMOS bulk and source are connected together by default which is strange by the way ).

Perhaps the same is valid for the PMOS ? Yes, this sounds weird to me, too, but there might be a technological reason for it. You could try and find it in AMI's PDK docu - or ask them directly.