Huge leakage for PIP(Poly1-Poly2) capacitor and antenna rule

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Hi,

We have our TSMC0.35um chip back and we found out there is huge leakage current for the PIP capacitor (>1mA). The inter-poly oxide should have been breakdown. Both poly1 and poly2 are connected to metal1 first and then use metal1 connect to the bond pad.

The MIM capacitor has tiedown as the leakage path during metal plasma etching, which will protect the MIM. For the PIP capacitor, do we really need some reversed-biased diode or tiedown to provide a leakage path? We didn't do the antenna check before tapeout, it's a stupid mistake.......

We have successful tapeout using ON semi 1.5um (2P1M) for PIP capacitor years ago. That time we don't have any protection for PIP capacitor it still works. I am guessing the reason here, please correct me if I am wrong:
Low metal layers say Metal1 or Metal2 use wet etch. ON 1.5um has only Metal1, so antenna check is not necessary. However, for TSMC0.35um, there are 4 metal layers. The metal3 and metal4 are plasma etching, which will bring problem for our design.

Anybody here has tapeout experiences with TSMC0.35um or AMS0.35? Thank you! [/b]

Added after 1 hours 23 minutes:

I think some people mentioned guard rings for the PIP capacitors. Will the guard rings help protect the capacitors during plasma etching?

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Did you catch up on the antenna check now? If so, did you get errors from it? If the PIP nodes are not connected to any transistor output, you could receive ARC error messages.

Added after 6 minutes:

For the PIP capacitor, do we really need some reversed-biased diode or tiedown to provide a leakage path?

Sure, if the ARC says so, and if the nodes aren't connected to transistor outputs (which would provide protection).

I think some people mentioned guard rings for the PIP capacitors. Will the guard rings help protect the capacitors during plasma etching?

Not at all!

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Did you catch up on the antenna check now? If so, did you get errors from it? If the PIP nodes are not connected to any transistor output, you could receive ARC error messages.

I didn't do the antenna check. It seems to me TSMC didn't offer antenna check rule file for designers. Or maybe it's some where I don't know?


Added after 6 minutes:

For the PIP capacitor, do we really need some reversed-biased diode or tiedown to provide a leakage path?

Sure, if the ARC says so, and if the nodes aren't connected to transistor outputs (which would provide protection).

Transistor output means MOSFET Drain/Source? How about reverse biased diode?

We don't have any connection to the capacitor plates. The plates are directly tied to the bond pad metal layers.

If we don't have any connection for the caps, the chance for the interpoly oxide break down should be very high during the plasma etching, right?

Can you justify my statement on the metal wet etch and plasma etch?

I think some people mentioned guard rings for the PIP capacitors. Will the guard rings help protect the capacitors during plasma etching?

Not at all![/quote]
Got it! No guard rings for the pip cap. Thank you for the input!

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

I didn't do the antenna check. It seems to me TSMC didn't offer antenna check rule file for designers. Or maybe it's some where I don't know?

Probably yes. If they do plasma etching (and I think it's always done for >2 metal layers), an ARC usually is a MUST, because all unprotected gates, PIPs & MIMs are prone to charge breakdown (which for MIMs & PIPs not necessarily is a permanent damage!).

Transistor output means MOSFET Drain/Source?

Yes.

How about reverse biased diode?

This one you need in case you have no connection to MOSFET Drain/Source (if the ARC reports an error on this node).

We don't have any connection to the capacitor plates. The plates are directly tied to the bond pad metal layers.

If we don't have any connection for the caps, the chance for the interpoly oxide break down should be very high during the plasma etching, right?

Yes, but this depends on the ARC rules (the ratio of metal route area to cap area) .

Can you justify my statement on the metal wet etch and plasma etch?

Yes, totally right!

Got it! No guard rings for the pip cap. Thank you for the input!

Guard rings are just for electrical screening the inside elements from outside influences (charge carriers, noise etc. trying to infiltrate via the silicon bulk) - or vice versa.

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

I didn't do the antenna check. It seems to me TSMC didn't offer antenna check rule file for designers. Or maybe it's some where I don't know?

Probably yes. If they do plasma etching (and I think it's always done for >2 metal layers), an ARC usually is a MUST, because all unprotected gates, PIPs & MIMs are prone to charge breakdown (which for MIMs & PIPs not necessarily is a permanent damage!).

Can you explain a little bit on why the MIMs and PIPs are not necessarily a permanent damage? Thanks.

Transistor output means MOSFET Drain/Source?

Yes.

How about reverse biased diode?

This one you need in case you have no connection to MOSFET Drain/Source (if the ARC reports an error on this node).

Of course, in the last failed tapeout we don't even have any reverse biased diodes. This means this is no leakage path for device protection.

We don't have any connection to the capacitor plates. The plates are directly tied to the bond pad metal layers.

If we don't have any connection for the caps, the chance for the interpoly oxide break down should be very high during the plasma etching, right?

Yes, but this depends on the ARC rules (the ratio of metal route area to cap area)

.
I didn't get the ARC rule from TSMC......
The bond pad is huge area 150um by 150um. The PIP cap with the bond pad is only 30 by 30um. The metal to cap ratio is pretty large. This could make the break down possibility very high.

Can you justify my statement on the metal wet etch and plasma etch?

Yes, totally right!

Got it! No guard rings for the pip cap. Thank you for the input!

Guard rings are just for electrical screening the inside elements from outside influences (charge carriers, noise etc. trying to infiltrate via the silicon bulk) - or vice versa.

You are excellent designer, awesome!!

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Can you explain a little bit on why the MIMs and PIPs are not necessarily a permanent damage?

Because of the same effect which usually "heals" the breakdown of so-called "self-healing" discrete metal-plastic-caps (search for self-healing or polypropylene). The energy of the electrical breakdown may vaporize the edges of the metal layers around the breakdown region, as well as the metal which possibly reaches the breakdown "via". After this, there's no connection anymore. But this happens - if ever - during the very breakdown event. If any metal connection is left, the "short-circuit" will remain forever. No hope for your cap, sorry! :-(

Of course, in the last failed tapeout we don't even have any reverse biased diodes. This means this is no leakage path for device protection.

This is what you would have needed!

I didn't get the ARC rule from TSMC......
The bond pad is huge area 150um by 150um. The PIP cap with the bond pad is only 30 by 30um. The metal to cap ratio is pretty large. This could make the break down possibility very high.

So the bond pad (+ M3,M4 routing) to PIP cap area is 25:1 . Usually the limit for ARC error generation is > 20:1 , so you would have got error messages from an ARC !

You are excellent designer, awesome!!

Thanks a lot! But all this came from layout, technology and process knowledge, not from design experience ;-)

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Because of the same effect which usually "heals" the breakdown of so-called "self-healing" discrete metal-plastic-caps (search for self-healing or polypropylene). The energy of the electrical breakdown may vaporize the edges of the metal layers around the breakdown region, as well as the metal which possibly reaches the breakdown "via". After this, there's no connection anymore. But this happens - if ever - during the very breakdown event. If any metal connection is left, the "short-circuit" will remain forever. No hope for your cap, sorry! :-(

I just checked online, the self-healing capacitor has electrolytic capacitor, and oil capacitor. Of course, for the on-chip cap, if the breakdown metal can be vaporized then there is no short path, it is also self-healing. However, if the breakdown happened at metal1, metal2 or metal3, not the top metal, deep in the metal layer stacks, then the chance for evaporation should be small, right?

This is what you would have needed!

For sure we will consider all these protection techniques. Last time we didn't do it because our previous design only have 1 metal layer (wet etch of course). This means we don't need to consider ARC before. And the transition to 0.35um is hard because we have no experiences on this process, thus the mistake on ARC is made......

So the bond pad (+ M3,M4 routing) to PIP cap area is 25:1 . Usually the limit for ARC error generation is > 20:1 , so you would have got error messages from an ARC !

When you calculate the ratio, you count the metal area as Area(M3) + Area(M4), or just the largest metal layer area, say Area(M4)?

You are excellent designer, awesome!! Thanks a lot! But all this came from layout, technology and process knowledge, not from design experience ;-)

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

I just checked online, the self-healing capacitor has electrolytic capacitor, and oil capacitor.

There exist also dry (non-electrolytic) self-healing caps: e.g. M-PP-M (PP=PolyPropylene, brand name MKP) or M-PC-M (PC=PolyCarbonate, brand name MKT) - but this is a bit off-topic, sorry!

Of course, for the on-chip cap, if the breakdown metal can be vaporized then there is no short path, it is also self-healing. However, if the breakdown happened at metal1, metal2 or metal3, not the top metal, deep in the metal layer stacks, then the chance for evaporation should be small, right?

Very true: At your PIP cap, the polysilicon either can't be vaporized, or - if it can - there's probably no chance for the polysilicon vapor to escape from the breakdown region.

When you calculate the ratio, you count the metal area as Area(M3) + Area(M4), or just the largest metal layer area, say Area(M4)?

There are antenna rules for each metal layer (to be ion etched). The individual layer rules always consider the ratio of the total current (means: at it is at that time) connection (routing) area to the area of the region which is prone to be damaged by the collected charge during the ion beam etch process.

In your case this means (if only M3 & M4 are ion-etched), that you would get ARC errors for M3 as well as for M4, because bonding pads usually own all these layers.

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

There exist also dry (non-electrolytic) self-healing caps: e.g. M-PP-M (PP=PolyPropylene, brand name MKP) or M-PC-M (PC=PolyCarbonate, brand name MKT) - but this is a bit off-topic, sorry!

Still very helpful and educational, thanks!

There are antenna rules for each metal layer (to be ion etched). The individual layer rules always consider the ratio of the total current (means: at it is at that time) connection (routing) area to the area of the region which is prone to be damaged by the collected charge during the ion beam etch process.

In your case this means (if only M3 & M4 are ion-etched), that you would get ARC errors for M3 as well as for M4, because bonding pads usually own all these layers.

So ARC errors for both M3 and M4 will be given. However the chance of getting M4 ARC error is larger than M3, because when ion-etching M4, the total metal routing area is Area(M3) + Area(M4), basically larger area than M3, right?

Then every PIP capacitor is damaged......The MOSFET gate oxide is also broken, because they are also directly connected to bond pad. And gate oxide is usually thinner than inter-poly oxide......
We really need to add some protection to our device. And we just realized this is the problem......

Thanks for your post, great help!

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

So ARC errors for both M3 and M4 will be given. However the chance of getting M4 ARC error is larger than M3, because when ion-etching M4, the total metal routing area is Area(M3) + Area(M4), basically larger area than M3, right?

Correct. For M4 probably ≈ 50:1 , because Pad(M3) = Pad(M4).

BTW: The fabs/foundries I worked with, use plasma/ion etching for all metal layers (eventually for the poly layer(s), too). However, you wouldn't necessarily get antenna error messages from poly and the lower metals in this case, as the connection to the pad isn't finished yet. E.g. during M2 etch, if you used reverse layer hopping: E.g. PO-M1-M2-M3-M2-M3-M4 : In this case - even as there is also M1 & M2 in the pad, during M2 etch the connection isn't yet established. The PO-M1-M2 antenna possibly stays below the 20:1 limit, thus won't provoke an error message. If the other M2 branch has no connection to breakdown-vulnerable areas, also no error message would be given. In your case, however, there seems a MOSFET gate to be connected to one of the branches.

Then every PIP capacitor is damaged......The MOSFET gate oxide is also broken, because they are also directly connected to bond pad. And gate oxide is usually thinner than inter-poly oxide......
We really need to add some protection to our device. And we just realized this is the problem......

You could perhaps use the std. protection of an (otherwise unused) I/O pad, if the additional capacitance is not a pb. Otherwise use an internal n+diode (on substrate), plus, maybe, an additional p+diode on n-well (which gives a better protection against the positive charge from the ion etch, because it limits the voltage to only about +1V during the etch process (during the etch, VDD is practically short-circuited to GND, whereas during operation there's no such voltage limitation, as the n-well is connected to VDD).

If the ARC should produce an error message already on a lower metal connection (when the connection to the pad isn't yet continuous, e.g. if reverse layer hopping is used, the protection circuitry in the pad is useless for the cap protection, of course), you'd need this/these internal diode(s) anyway.

Good luck for the next shuttle!
erikl

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Correct. For M4 probably ≈ 50:1 , because Pad(M3) = Pad(M4).

BTW: The fabs/foundries I worked with, use plasma/ion etching for all metal layers (eventually for the poly layer(s), too). However, you wouldn't necessarily get antenna error messages from poly and the lower metals in this case, as the connection to the pad isn't finished yet. E.g. during M2 etch, if you used reverse layer hopping: E.g. PO-M1-M2-M3-M2-M3-M4 : In this case - even as there is also M1 & M2 in the pad, during M2 etch the connection isn't yet established. The PO-M1-M2 antenna possibly stays below the 20:1 limit, thus won't provoke an error message. If the other M2 branch has no connection to breakdown-vulnerable areas, also no error message would be given. In your case, however, there seems a MOSFET gate to be connected to one of the branches.

Here I have a question: if we use the metal jumper PO-M1-M2-M3-M2-M3-M4, then during M2 etch, the oxide is safe because PO-M1-M2 area is still small. However, during M3 etch, both two branches of M2 are still connected together through M3. Thus if we estimate the area ratio, the total area of metal is still much larger than oxide. Or, maybe, the antenna ratio is just for the "current" metal layer area to oxide, excluding other connected metal layers?

I am kind of confused here about how to calculate the antenna ratio, I checked a lot of website and books. Some of them say it's the total peripheral area of conductor connected to the oxide; while some other say it's the conducting area exposed to the plasma, say during M3 etch, only the M3 layer area counts.
Can you explain a little more on this?
Check this link: https://www.mosis.com/Technical/Designrules/guidelines.html
On the MOSIS website, their definition:"a figure of exposed conductor area to transistor gate area ratio is determined which guarantees Time Dependent Dielectric Breakdown (TDDB) reliability requirements for the fabricator".
PS: I think MOSIS defined both conservative and less-conservative calculation method. The conservative one considers the total area: PO+M1+M2+M3.....

You could perhaps use the std. protection of an (otherwise unused) I/O pad, if the additional capacitance is not a pb. Otherwise use an internal n+diode (on substrate), plus, maybe, an additional p+diode on n-well (which gives a better protection against the positive charge from the ion etch, because it limits the voltage to only about +1V during the etch process (during the etch, VDD is practically short-circuited to GND, whereas during operation there's no such voltage limitation, as the n-well is connected to VDD).

This is good. Some people also mentioned using reverse biased diode-connected transistors.
Is there any limitation for the diode area? say as large as possible?

If the ARC should produce an error message already on a lower metal connection (when the connection to the pad isn't yet continuous, e.g. if reverse layer hopping is used, the protection circuitry in the pad is useless for the cap protection, of course), you'd need this/these internal diode(s) anyway.

Good luck for the next shuttle!
erikl

Thanks!
There is also an interesting article: **broken link removed**

 

[erikl]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

Here I have a question: if we use the metal jumper PO-M1-M2-M3-M2-M3-M4, then during M2 etch, the oxide is safe because PO-M1-M2 area is still small. However, during M3 etch, both two branches of M2 are still connected together through M3. Thus if we estimate the area ratio, the total area of metal is still much larger than oxide. Or, maybe, the antenna ratio is just for the "current" metal layer area to oxide, excluding other connected metal layers?

No, always the cumulative connected area should be used. Charges are mobile and distribute themselves on the total connected node area.

I am kind of confused here about how to calculate the antenna ratio, I checked a lot of website and books. Some of them say it's the total peripheral area of conductor connected to the oxide; while some other say it's the conducting area exposed to the plasma, say during M3 etch, only the M3 layer area counts.
Can you explain a little more on this?

As noted above, most antenna rules consider currently (i.e. at the individual process time) cumulative connected area. Anyway, such a PID hazard estimation (i.e. using the area ratio) is a rather coarse method, IMHO, as you also might find after reading the eetimes article. There's so much uncertainty due to the possible latent connectivity, edge-only (not area-dependent) charge collection, and time dependency of all these effects, that the area ratio method can only result in a very raw estimation.

The end of the story? If in doubt, provide your own internal protection diode(s)!

Check this link: https://www.mosis.com/Technical/Designrules/guidelines.html
On the MOSIS website, their definition:"a figure of exposed conductor area to transistor gate area ratio is determined which guarantees Time Dependent Dielectric Breakdown (TDDB) reliability requirements for the fabricator".
PS: I think MOSIS defined both conservative and less-conservative calculation method. The conservative one considers the total area: PO+M1+M2+M3.....

All the antenna rules I know use this "conservative" (cumulatively connected) calculation method. Charges are mobile!

Some people also mentioned using reverse biased diode-connected transistors.

This is the standard protection, if a gate (or a MIM, a PIP) is supplied by an output: the inherent reverse diode of any MOSFET then provides the necessary protection.

Is there any limitation for the diode area? say as large as possible?

Quite the contrary: A minimum size diode will do the job. The currents resulting from the charge collection are minimal.

There is also an interesting article: **broken link removed**

Very good article! Allows excellent insight into the phenomenon. Thank you!

erikl

 

[pippip]

Re: Huge leakage for PIP(Poly1-Poly2) capacitor and antenna

The end of the story? If in doubt, provide your own internal protection diode(s)!

Thanks a lot for the input I will place the internal diode for large area metal anyway, regardless the metal jumper.

All the antenna rules I know use this "conservative" (cumulatively connected) calculation method. Charges are mobile!

Totally understand!

Quite the contrary: A minimum size diode will do the job. The currents resulting from the charge collection are minimal.

This is different from ESD protection, which pursue large current path.

Very good article! Allows excellent insight into the phenomenon. Thank you!

You are welcome!