How will D flip-flop output depend on clock?

[santuvlsi]

Dear friends,

I have two D flip flop with Q1 as output of First F/F and Q2 of second F/F

i have given D as 1

What will be the output Q1 and Q2 depaending on Clock

Pls explain

santu

 

[carv_13]

Re: about flip flop

After 2 clock cycles, the output of 2nd flipflop will be 1. At the end of first clock cycle, the 1 at D will be available at q of the first flop and this 1 will be captured by the 2nd flipflop at the second cycle and will be available at q of the second flipflop.
The value at q of the second flipflop during the first clock cycle is an invalid value or a value that should not be used in any other logic. This is the basis of pipelining.
Please do correct me if I am wrong.

-Aravind

 

[santuvlsi]

Re: about flip flop

Dear dude,

My clock is a pulse train which has postivie and neagtive cycle.

Now on positive cycle first F/F will give Q as 1,
Then the neagtive cycle comes now what will be condition or Q1 and Q2

Santu

 

[amitjagtap]

about flip flop

FF is edge triggered. so clock active edge will be either +ve or - ve. If the FF is +ve edge triggered. then for first +ve edge output Q1 will be one and Q2 will be at its previous state. At -ve edge the outputs Q1 & Q2 will be maintained as it is. At second +ve clock edge Q1 will be D (depending on input D) and Q2 will be 1.

 

[carv_13]

Re: about flip flop

During the negative clock cycle, FF1 would continue to store 1 which it had latched during the positive cycle and FF2 would now hold the value that was previously held by FF1. Am I missing some condition here?.