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How to Writing this statment in VHDL

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cysco

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In verilog,
I can write like this:

assign next_lookup = lookup[15:0] & {16{lookup_en}} // lookup_en is 1 bit.

How to have the same statement in VHDL??
 

rca

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one way:
FOR i IN 0 TO 15 GENERATE
BEGIN
next_lookup <= lookup AND lookup_en;
END GENERATE;

---------- Post added at 10:57 ---------- Previous post was at 10:54 ----------

an other way:
SIGNAL vect_lookup_en : STD_LOGIC_VECTOR(15 DOWNTO 0);

vect_lookup_en <= (OTHERS=>lookup_en);
next_lookup <= lookup AND vect_lookup_en;
 

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