How to write vhdl code for d/e <= (a/b + c/d)

[harerama]

Hi.

How to write RTL vhdl code for d/e <= (a/b + c/d) this statment.


Thanks in advance

Regards
Raghavendra

 

[TrickyDicky]

quite easily using ieee.numeric_std package:

e <= d / (a/b + c/d);

but dont expect to get a decent fmax.

For a reasonable solution, you will needed to use pipelined divider ip blocks.

 

[harerama]

Thanks Tricky Dicky.

 

[FvM]

Sorry, but I can't read a clear meaning into the original expression d/e <= (a/b + c/d). And not reproduce the suggested transformation. If it's intended to solve the equation for a specific variable, it would be stated in the problem, I presume.

 

[harerama]

Thanks FvM. Actuall i plan to write RTL VHDL code for addition(+) of rational numbers and result should not be in the form of fraction.

 

[FvM]

result should not be in the form of fraction

Rather than in what form? I guess you know that
a/b + c/d = (a*d + c*b)/b*d
So you can get an exact rational result.

 

[harerama]

Thanks..ya i know what you said.I little bit confusion how to write vhdl code for this.

 

[FvM]

By now, you didn't specify which numbers are input and outputs, and what's there numeric range, either as bit width of signed/unsigned or integer ranges. TrickyDicky assumed, that e is the intended output signal, which may be right, but doesn't answer about the intended number format.

 

[harerama]

Thanks...I am totally newbie on VHDL please guide me how to write a program addition of two rational numbers, result should be in the form of rational number only.