how to write the ucf file in xilinx for array variables

in the main program i have some output variables which are declared as array.
ex: chain1, chain2ut array
Each bvariable stores 7 bits.ie: chain[0] to chain [7] and similarly for chain2.
If we use std_logic_vector , in ucf file we can write it as
NET "chain<0>" LOC "p23"
NET "chain<1>" LOC "p24" AND SO ON
But in the case of array how can we write the ucf.
plz reply

I assume you have an array of std_logic_vectors? I have no idea what your statement about bvariables means. What's a bvariable? And if you have chain[0] to chain[7] that's 8 bits, not 7.

So, ASSUMING chain1 is an array of std_logic_vectors,you would write:

NET chain1[0][0] LOC "p23"--first bit of first vector
NET chain1[0][1] LOC "p24"--second bit of first vector
NET chain1[1][0] LOC "p48"--first bit of second vector

But now that I think about it, I'm not sure you can actually use an array as an output port

The main entity is as follows


can u plz giv me the ucf format

- - - Updated - - -

The main entity is as follows


can u plz giv me the ucf format

jincyjohnson said:

The main entity is as follows

Code:

library ieee;
    use ieee.std_logic_1164.all;
    
    Package my_pack1 is    
        
        type arr1 is array(0 to 15) of std_logic_vector(0 to 7);       
        type arr2 is array(0 to 31) of std_logic_vector(0 to 7);
    
    end package;
    
    
library ieee;
    
    use ieee.std_logic_1164.all;
    use work.my_pack1.all;
    
entity patternpwr is
    port(clk1:in std_logic;
         clk2:in std_logic;        
         seed:in std_logic_vector(0 to 4);     
         chain1,chain2,chain3,chain4:out arr1
         );
     end patternpwr;

can u plz giv me the ucf format

- - - Updated - - -

The main entity is as follows

Code:

library ieee;
    use ieee.std_logic_1164.all;
    
    Package my_pack1 is    
        
        type arr1 is array(0 to 15) of std_logic_vector(0 to 7);       
        type arr2 is array(0 to 31) of std_logic_vector(0 to 7);
    
    end package;
    
    
library ieee;
    
    use ieee.std_logic_1164.all;
    use work.my_pack1.all;
    
entity patternpwr is
    port(clk1:in std_logic;
         clk2:in std_logic;        
         seed:in std_logic_vector(0 to 4);     
         chain1,chain2,chain3,chain4:out arr1
         );
     end patternpwr;

can u plz giv me the ucf format

Click to expand...

I thought I did. What more do you want???

the pattern is generated as follows (example only)

chain1 [11110000 11111000------]
chain2 [11000000 11100000-----]
chain3 [11100000 11100000---]
chain4 [10101110 11101110-----]
here each vector in a chian are of 8 bts.
i didn't get

NET chain1[0][0] LOC "p23"--first bit of first vector
NET chain1[0][1] LOC "p24"--second bit of first vector
NET chain1[1][0] LOC "p48"--first bit of second vector
plz reply
thanks 4 ur reply and valuable suggestion

jincyjohnson said:

the pattern is generated as follows (example only)

chain1 [11110000 11111000------]
chain2 [11000000 11100000-----]
chain3 [11100000 11100000---]
chain4 [10101110 11101110-----]
here each vector in a chian are of 8 bts.
i didn't get

NET chain1[0][0] LOC "p23"--first bit of first vector
NET chain1[0][1] LOC "p24"--second bit of first vector
NET chain1[1][0] LOC "p48"--first bit of second vector
plz reply
thanks 4 ur reply and valuable suggestion

Click to expand...

I guess it is like this:

Take Chain1 for example - chain1 [11110000 11111000------]. Then pin assignment will be like this considering the vector info.

NET chain1[0][0] LOC "p23"--first bit of first vector
NET chain1[0][1] LOC "p24"--second bit of first vector
NET chain1[0][2] LOC "p25"--third bit of first vector
NET chain1[0][3] LOC "p26"--fourth bit of first vector
NET chain1[0][4] LOC "p27"--fifth bit of first vector
NET chain1[0][5] LOC "p28"--sixth bit of first vector
NET chain1[0][6] LOC "p29"--seventh bit of first vector
NET chain1[0][7] LOC "p30"--eigth bit of first vector

NET chain1[1][0] LOC "p31"--first bit of second vector
NET chain1[1][1] LOC "p32"--second bit of second vector
NET chain1[1][2] LOC "p33"--third bit of second vector
NET chain1[1][3] LOC "p34"--fourth bit of second vector
NET chain1[1][4] LOC "p35"--fifth bit of second vector
NET chain1[1][5] LOC "p36"--sixth bit of second vector
NET chain1[1][6] LOC "p37"--seventh bit of second vector
NET chain1[1][7] LOC "p38"--eigth bit of second vector

I don't know whether the board has so many pins but this is what I understood.

totally it generates 16 number of 8 bit vectors. So it cannot be done it spartan 3E as it does not contain the enough number of input pins. can u suggest another option plz.

jincyjohnson said:

totally it generates 16 number of 8 bit vectors. So it cannot be done it spartan 3E as it does not contain the enough number of input pins. can u suggest another option plz.

Click to expand...

Um, use a different FPGA?