Oct 21, 2005 #1 T tarkyss Full Member level 6 Joined Aug 1, 2005 Messages 340 Helped 26 Reputation 52 Reaction score 8 Trophy points 1,298 Location China Activity points 4,162 b=a{1'b1}; a is not a constant
Oct 21, 2005 #2 K Kukaz Member level 1 Joined May 9, 2001 Messages 33 Helped 3 Reputation 6 Reaction score 2 Trophy points 1,288 Activity points 240 b <= a(1); IMHO ) P.S. If b is STD_LOGIC and a - STD_LOGIC_VECTOR !!!
Oct 21, 2005 #3 T tarkyss Full Member level 6 Joined Aug 1, 2005 Messages 340 Helped 26 Reputation 52 Reaction score 8 Trophy points 1,298 Location China Activity points 4,162 b is std_logic_vector for example a=4 then b=1111
Oct 21, 2005 #4 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 I don't know much VHDL, but in Verilog I think b=a{1'b1}; is a syntax error. Maybe you mean b={a{1'b1}}; but that's an error too if the repetition multiplier a is not a constant.
I don't know much VHDL, but in Verilog I think b=a{1'b1}; is a syntax error. Maybe you mean b={a{1'b1}}; but that's an error too if the repetition multiplier a is not a constant.
Oct 21, 2005 #5 T tarkyss Full Member level 6 Joined Aug 1, 2005 Messages 340 Helped 26 Reputation 52 Reaction score 8 Trophy points 1,298 Location China Activity points 4,162 sorry, a is constan defined with 'define
Oct 21, 2005 #6 K Kukaz Member level 1 Joined May 9, 2001 Messages 33 Helped 3 Reputation 6 Reaction score 2 Trophy points 1,288 Activity points 240 for I in 0 to a-1 loop b(I) <= '1'; end loop; P.S. a is CONSTANT !!!
Oct 21, 2005 #7 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 Or do something like this: b <= NOT (ShiftLeft("1111111111111111", a)) ;
Oct 21, 2005 #8 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 tarkyss said: sorry, a is constan defined with 'define Click to expand... Try using VHDL aggregates for it. Read FAQ: www.vhdl.org/comp.lang.vhdl/ If this "a" defines the size of "b", then simply: b <= (others => '1'); HTH Ajeetha www.noveldv.com
tarkyss said: sorry, a is constan defined with 'define Click to expand... Try using VHDL aggregates for it. Read FAQ: www.vhdl.org/comp.lang.vhdl/ If this "a" defines the size of "b", then simply: b <= (others => '1'); HTH Ajeetha www.noveldv.com