fsm verilog example parameter
You can add some for debug conversion as below
// synopsys translate_off
reg [12*8-1:0] curr_state_name; // one char need 8-bit, therefore curr_state_name can contain 12 chars
always @(curr_state) // curr_state is your FSM registers
begin
case(curr_state)
STATE_0: curr_state_name = "string_0"; // string_0 is the the name you want to show
STATE_1: curr_state_name = "string_1";
STATE_2: curr_state_name = "string_2";
STATE_3: curr_state_name = "string_3";
endcase
end
// synopsys translate_on
After you do so, you can probe the curr_state_name instead of curr_state when you watch the waveform.
(It is supposed that the waveform viewer can display ASCII type)
Regards,
Jarod