How to Write "Literate" FSM in Verilog HDL?

[cevitamic]

verilog fsm parameter

In VHDL, the states of a FSM can be defined as enumerate types, so that in ModelSim, literate state names can be shown. How can I do the similar thing in Verilog HDL?

 

[rprince006]

verilog `define fsm

You cannot do the same thing in Verilog as far as I know.
However, you can define the state coding using parameter statement.

Regards,

 

[jarodz]

fsm verilog example parameter

You can add some for debug conversion as below


// synopsys translate_off
reg [12*8-1:0] curr_state_name; // one char need 8-bit, therefore curr_state_name can contain 12 chars

always @(curr_state) // curr_state is your FSM registers
begin
case(curr_state)
STATE_0: curr_state_name = "string_0"; // string_0 is the the name you want to show
STATE_1: curr_state_name = "string_1";
STATE_2: curr_state_name = "string_2";
STATE_3: curr_state_name = "string_3";
endcase
end
// synopsys translate_on


After you do so, you can probe the curr_state_name instead of curr_state when you watch the waveform.
(It is supposed that the waveform viewer can display ASCII type)

Regards,
Jarod

 

[masai_mara]

Or you can use system verilog which supports enumerated types.

 

[power-twq]

you can use parameter to define state in verilog hdl.

for example, if you want to use four state named as

s1, s2, s3, s4,

you can define them use parameter as follow:

parameter s1 = 0;
parameter s2 = 1;
parameter s3 = 2;
parameter s4 = 3;

In VHDL, the states of a FSM can be defined as enumerate types, so that in ModelSim, literate state names can be shown. How can I do the similar thing in Verilog HDL?

 

[srik_naidu]

hi,
refer to verilog hdl by samir palnitkar it will helpful to you.

with regards,
srik.

 

[jjww110]

you can define them use parameter or use define