how to write correctly a testbench of the top module

[chibijia]

recently i write a code which embrace two subside modules,such as
module1 module segbcd(data,clk,rst,seg_out) where data is 8bits input ;clk,rst are 1bit input,seg_out is 8bits output,and
module2 module counter(s,sc,sn,rst,clk,data_sn,data)
where s,sc,sn,rst,clk are 1bit input ,data_sn is 8bits input,data is 8 bits output;
and the clk and rst can be the common node.and the output of the module2-data is the input of module1-data.
can anybody tell me how to write a correct testbench for this design!
help!!!

 

[ckaa]

Here's a quick testbench. It may have minor erros. Check it out though and let me know if it works for you!

module_tb();
reg clk, reset;
wire[7:0] data_sn, data, seg_out;
wire s, sc, sn;

//adjust your delay according to your reset pulse width
// Also provide stimuli for your s, sc, sn inputs according to your design
initial begin
clk = 0;
reset = 0;
#20 reset = 1;
#20 reset = 0;

end

//determine your clock period and adjust the delay below
always #50 clk = ~clk;


segbcd segbcd_inst(
data(data),
clk(clk),
rst(reset),
seg_out(seg_out)
);

counter counter_inst(
s(s),
sc(sc),
sn(sn),
rst(reset),
clk(clk),
data_sn(data_sn),
data(data)
);

endmodule