i want to write a code in vhdl to count a input signal for a particular time duration
for eg. i have a window size of 0 to 99999sec
in this user sets up a input of 10sec
how to write a vhdl code which can count the pulses for 10sec and then stop
i have a clock of 3Mhz
Divide the clock, use that as your clock for a counter and start counting, when the signal goes active, stop counting and save the data into a register, repeat the same thing over and over.
Divide the clock, use that as your clock for a counter and start counting, when the signal goes active, stop counting and save the data into a register, repeat the same thing over and over.
Well, I think TrickyDicky is only repeating a simple FPGA design rule "don't use divided clocks".
But I agree about "not jumping into conclusions", because it may be the case, that the complete design can be run by the divided clock only. Then there's no issue with clock dividers.
If you however want the "fast" respectivly less slow 3 MHz clock e.g. to process input pulses, thenthe design should better operate with a single clock and divided clock enable.
either:
1.) purchase an FPGA with this feature, such as a Spartan3-AN.
2.) purchase an FPGA that can read from an external Flash. Most Xilinx parts have this feature (see the configuration guide).
3.) use a second microcontroller that can program the FPGA as well as read the FPGA code from another source at boot.