How to write a VHDL code which can count the pulses for 10sec and then stop?

[rob007]

i want to write a code in vhdl to count a input signal for a particular time duration
for eg. i have a window size of 0 to 99999sec
in this user sets up a input of 10sec
how to write a vhdl code which can count the pulses for 10sec and then stop
i have a clock of 3Mhz

 

[farhada]

Re: fpga code

Divide the clock, use that as your clock for a counter and start counting, when the signal goes active, stop counting and save the data into a register, repeat the same thing over and over.

 

[TrickyDicky]

Re: fpga code

Divide the clock, use that as your clock for a counter and start counting, when the signal goes active, stop counting and save the data into a register, repeat the same thing over and over.

Unless you're building an ASIC, using a counter to clock and another circuit opens you up to all sorts of timing problems.

Yes diving the clock with a counter, but us the output as an enable - not another clock.

 

[farhada]

Re: fpga code

Dude, where in my message did you find "use a counter as a clock"?

Please read the message before jumping into conclusion and lecturing people.

You can divide the clock using a clock divider inside the FPGA (depending on what type he is planning to use Altera, Xilinx, Actel etc).

Is it that difficult to understand?

 

[FvM]

Re: fpga code

Well, I think TrickyDicky is only repeating a simple FPGA design rule "don't use divided clocks".

But I agree about "not jumping into conclusions", because it may be the case, that the complete design can be run by the divided clock only. Then there's no issue with clock dividers.

If you however want the "fast" respectivly less slow 3 MHz clock e.g. to process input pulses, thenthe design should better operate with a single clock and divided clock enable.

 

[jatink007]

Re: fpga code

but how to divide the clock to that extent?????

---------- Post added at 05:51 AM ---------- Previous post was at 05:47 AM ----------

to divide the clock for say 10 sec a large chain will be required!

 

[FvM]

Re: fpga code

to divide the clock for say 10 sec a large chain will be required!

25 registers and a number of LEs for the feedback in case of a binary counter. Not large in terms of FPGA resources.

 

[jatink007]

Re: fpga code

how to store the code in the fpga so that it retains it even after power off?

 

[permute]

Re: fpga code

either:
1.) purchase an FPGA with this feature, such as a Spartan3-AN.
2.) purchase an FPGA that can read from an external Flash. Most Xilinx parts have this feature (see the configuration guide).
3.) use a second microcontroller that can program the FPGA as well as read the FPGA code from another source at boot.