How to write a filter description that only lets positive pulses pass?

[Gman33842016]

Hi,

Can anybody gives some clue about how to write a filter description that only lets positive pulses of exactly 4 ns and 8 ns to pass through to the output??

It is something to do about inertial delay ?


The Structure of my code something like this

ENTITY b_filter IS
GENERIC (w1 : TIME := 4 NS; w2 : TIME := 8 NS);
PORT (x : IN BIT; y : OUT BIT);
END b_filter;

ARCHITECTURE behavioral OF b_filter IS
-------
BEGIN
------
END behavioral;


Thank you.

 

[mohamadzn]

Pulse Delay

this code is not synthesizable.
you shoud create a shif register and with a clk domain of 1ns shift the input pulse to the shift register then you have the 4ns pulse in the 4th bit and 8 in the 8th.
if (clk = '1' and clk'event) then
shift (8 downto 0) <= shift (7 downto 0) & input;