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what do you mean by delay... do you want to write a test bench... or you want a module which delays a signal... 9if you want to write a test bench then you can use
wait for 50ns;command...
be clear wth your question....
Delay is modeled by WAIT statement in VHDL .. but keep in mind that it's not synthesizable .. on the other hand, you can model a delay of one-clock cycle by designing a flip flop (synthesizable) ..
Another possibility:
Some FPGAs provide special time delay features, such as the adjustable IODELAY in a Virtex-5 I/O block. To use this special hardware delay, you must instantiate a special Xilinx module. The synthesis tools won't infer the delay from conventional HDL delay syntax.
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