fcc124
Newbie level 2
Hi all,
I have a question about using Verilog to instantiate a VHDL entity with generic parameter.
VHDL entity:
entity xxx is
generic(a,b : integer);
port(
...
I use two method to instantiate this VHDL entity in Verilog.
1)
genvar i,j;
generate
for(i=1; i < N; i=i+1) begin :
for (j=1; j < M; j=j+1) begin :
xxx #(.a(i), .b(j)) xxx_inst();
2)
genvar i,j;
generate
for(i=1; i < N; i=i+1) begin :
for (j=1; j < M; j=j+1) begin :
xxx #(i, j) xxx_inst();
Problem in simulation with ncverilog:
In the first method, parameter a does not get the value of i, but b gets the value of j. However, in the second method, parameter a gets the value of i, but b does not get the value of j. I don't know the reason.
Does anybody know how to instantiate a VHDL entity with generic parameter in Verilog correctly?
Thanks!
I have a question about using Verilog to instantiate a VHDL entity with generic parameter.
VHDL entity:
entity xxx is
generic(a,b : integer);
port(
...
I use two method to instantiate this VHDL entity in Verilog.
1)
genvar i,j;
generate
for(i=1; i < N; i=i+1) begin :
for (j=1; j < M; j=j+1) begin :
xxx #(.a(i), .b(j)) xxx_inst();
2)
genvar i,j;
generate
for(i=1; i < N; i=i+1) begin :
for (j=1; j < M; j=j+1) begin :
xxx #(i, j) xxx_inst();
Problem in simulation with ncverilog:
In the first method, parameter a does not get the value of i, but b gets the value of j. However, in the second method, parameter a gets the value of i, but b does not get the value of j. I don't know the reason.
Does anybody know how to instantiate a VHDL entity with generic parameter in Verilog correctly?
Thanks!