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How to use the variable in VHDL ?

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GoodMan

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Hi all,

As title!!
Plz share your experience !

have a nice day!
 

silencer3

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Variables in verilog
1. simulation
For simulation the difference between signals and variable is truly evident. variable gets its value immediately but signal gets its new value after all DELTA time steps only.

2. Synthesis
For synthesis, one cannot c;learly say that variable will not be synthesized. It all depends on coding. but it better to follow some rules (ex: variable in FOR loops, usage of variables for memeory, ....etc) for proper usage of variables. In the above cases variables will give better results in synthesis when compared to signals. But signals anyway are used for all design implementations. So, synthesys point fo view it is very diffcicult to distuinguish between signals and variables, it all depends on coding.
 

omara007

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GoodMan said:
Hi all,

As title!!
Plz share your experience !

have a nice day!

Process (clk,reset_n)
variable x : integer := 0;
begin
if reset_n = '0' then

elsif rising_edge(clk) then
-- assign any value to the variable
end if;
 

s8319

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signal vs. variable
(1) Physical meaning
Signals represent physical interconnect (wire) that communicate between processes (functions).

Variable do not has physical meanings, not exist in real circuits, mainly used for simulation, represent local storage. Like a variable in C or Pascal, a variable in VHDL carries with it only one piece of information: its current value.

(2) Delay
Signals assignment can have delays, update at the end of the process.It is important to realize that even without an after clause, all signal assignments occur with some infinitesimal delay, known as delta delay. Technically, delta delay is of no measurable unit, but from a hardware design perspective you should think of delta delay as being the smallest time unit you could measure, such as a femtosecond.

Variable assignments are updated immediately

(3) Defination
Signal can not be defined in process and subprogram(including fuction and procedure), must be defined outside them
Variable can only be difined in process and subprogram(including fuction and procedure),should not be defined outside.


The following is two classic examples to explain to differents between signal and variable
----------For signals-----------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY C1 is
PORT( IP: in std_logic;
CP: in std_logic;
OP: out std_logic
);
END C1;
ARCHITECTURE a OF C1 IS
signal d : std_logic;
BEGIN
process(CP,IP)
begin
if CP'event and CP='1' then
D<=IP;
OP<=D;
end if;
end process;
END a;
_________For variable_________________________
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY C2 is
PORT( IP: in std_logic;
CP: in std_logic;
OP: out std_logic
);
END C2;
ARCHITECTURE a OF C2 IS
BEGIN
process(CP,IP)
variable D: std_logic;
begin
if CP'event and CP='1' then
D:=IP;
OP<=D;
end if;
end process;
END a;
 

mystique_unbound

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Variable in VHDL has sequential property . While the process is executing signal changes are effected after a clock if it is a clocked process . But variable on the other hand changes simultanously at the same time interval . They are similar to wire in real circuits and they are used to model gated input say Din is controlled through some combinational ckt and latched .

Variable are highly useful if we want to write C type coding
 

elecs_gene

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hi
then do u mean to say,that variables are not synthesizable in vhdl???
 

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