How to use the define parameter of verilog in debussy?

[richardhuang]

verilog define parameter

in my verilog code, i use "ifdef **" to define some module, but how can i make debussy find the correct module ?how to tell debussy the define infomation?

 

[nand_gates]

debussy ifdef

Debussy understands `define You should include `defines in one file and pass
it to debussy!
Here is an example!
Debussy will show you OR gate

`define __OR 1
module alu(
   // Outputs
   y, 
   // Inputs
   a, b
   );
   input a, b;
   output      y;

`ifdef __OR
   assign      y = a|b;
`else
   assign      y = a&b;
`endif
endmodule

Debussy will show you and gate!

module alu(
   // Outputs
   y, 
   // Inputs
   a, b
   );
   input a, b;
   output      y;

`ifdef __OR
   assign      y = a|b;
`else
   assign      y = a&b;
`endif
endmodule