peen1
Member level 2
ncverilog sdf
I have these followng files
test.sdf
a.v,
testbench.v
The testbench.v file instantiates a and test. Everything compile in Nc-launch/verilog and I also get test.sdf.X file but during ncelab it says can't find design test. Also it does not produce a snapshot for simulation.
I have saved test.v in a seperate location and do not compile that.
Does anyone know how to use sdf files in nc-verilog simulation?
Thanks
I have these followng files
test.sdf
a.v,
testbench.v
The testbench.v file instantiates a and test. Everything compile in Nc-launch/verilog and I also get test.sdf.X file but during ncelab it says can't find design test. Also it does not produce a snapshot for simulation.
I have saved test.v in a seperate location and do not compile that.
Does anyone know how to use sdf files in nc-verilog simulation?
Thanks