subramanyam
Member level 3
hii,
I am doing a project on memory controller in which i am trying to implement a design using fifos and FSMs . this design acts as an interface between the fast peripherals sending burst of data , and a slow memory.
i have implemented the design in VHDL. whenever the external device request read into memory, my design will put the address on the address bus of memory and, for write data it put the address on address bus and data on data bus .
my problem is, i want to implement the memory using linked lists in C language.
so whenever it takes that address and data how can i receive them into my vhdl testing program.
And how can i link these two, plz any one help me regarding this.
thank you,
subbu
I am doing a project on memory controller in which i am trying to implement a design using fifos and FSMs . this design acts as an interface between the fast peripherals sending burst of data , and a slow memory.
i have implemented the design in VHDL. whenever the external device request read into memory, my design will put the address on the address bus of memory and, for write data it put the address on address bus and data on data bus .
my problem is, i want to implement the memory using linked lists in C language.
so whenever it takes that address and data how can i receive them into my vhdl testing program.
And how can i link these two, plz any one help me regarding this.
thank you,
subbu