How to use LVDS inputs (spartan-3e)?

[Tayta Inti]

I don’t have any experience using LVDS and I have problems with implementation. I checked quite a few examples on the Internet but everyone doesn’t work. I get errors all the time… I suppose that my troubles are really trivial and probably should resolve my problems one good example of implementation.

I use Spartan-3e and ISE 13.1.

My code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity TEST is
Port ( SYS_CLK2 : in std_logic; -- main clock
S_RST_N : in std_logic; -- async reset
DATA_P : in std_logic;
DATA_N : in std_logic;
WY : out std_logic);
end TEST;

architecture Behavioral of TEST is

begin

IBUFDS_1 : IBUFDS
-- generic map (
-- IOSTANDARD => "MINI_LVDS_25")
port map (
O => WY,
I => DATA_P,
IB => DATA_N);
end Behavioral;​

My UCF-file:

NET "DATA_P" LOC = "B4" | IOSTANDARD = MINI_LVDS_25 ;
NET "DATA_N" LOC = "A4" | IOSTANDARD = MINI_LVDS_25 ;
NET "SYS_CLK2" LOC="C9" | IOSTANDARD = LVCMOS33;
NET "S_RST_N" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; # SW0
NET "WY" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;​

I tried to check almost everyone solution which I looked for in the WEB but always I have some errors, for example like this:

ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single DIFFSI component because the site type selected is not compatible. The
component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
DIFFSI was chosen because the IO contains symbols and/or properties
consistent with input differential slave usage. Please double check that the
types of logic elements and all of their relevant properties and
configuration options are compatible with the physical site type of the
constraint.

Summary:
Symbols involved:
PAD symbol "DATA_N" (Pad Signal = DATA_N)
SlaveBuffer symbol "IBUFDS_1/SLAVEBUF.DIFFIN" (Output Signal =
IBUFDS_1/SLAVEBUF.DIFFIN)
Component type involved: DIFFSI
Site Location involved: A4
Site Type involved: DIFFM

ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single DIFFMI component because the site type selected is not compatible. The
component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
DIFFMI was chosen because the IO contains symbols and/or properties
consistent with input differential master usage. Please double check that the
types of logic elements and all of their relevant properties and
configuration options are compatible with the physical site type of the
constraint.

Summary:
Symbols involved:
PAD symbol "DATA_P" (Pad Signal = DATA_P)
DIFFAMP symbol "IBUFDS_1/IBUFDS" (Output Signal = WY_OBUF)
Component type involved: DIFFMI
Site Location involved: B4
Site Type involved: DIFFS​

Thank you in advance.
Best Regards.

 

[Fl1pFl0p]

I am guessing you are using a BGA part and these pins are located in the same bank (bank0). All pins this bank must use the same I/O standard. Try making all pins in the same bank LVCMOS33 or MINI_LVDS_25. If you need these I/O move all LVCMOS33 and LVTTL to other banks.

 

[Tayta Inti]

I am guessing you are using a BGA part and these pins are located in the same bank (bank0). All pins this bank must use the same I/O standard. Try making all pins in the same bank LVCMOS33 or MINI_LVDS_25. If you need these I/O move all LVCMOS33 and LVTTL to other banks.

Thanks for help.
My problem was really trivial, I had wrong order of ports in UCF-file.
DATA_P should have LOC = "A4" not LOT="B4".

My working UCF-file:

NET "DATA_P" LOC = "A4" | IOSTANDARD = MINI_LVDS_25 | SLEW = FAST | DRIVE = 8 ;
NET "DATA_N" LOC = "B4" | IOSTANDARD = MINI_LVDS_25 | SLEW = FAST | DRIVE = 8 ;

NET "SYS_CLK2" LOC="C9" | IOSTANDARD = LVCMOS33;
NET "S_RST_N" LOC = "L13" | IOSTANDARD = LVCMOS33 | PULLUP ; # SW0
NET "WY" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;​

Best Regards.

 

[yadog]

basically,in a certain io bank,you should use the same referrence voltage

if you obey the rule,it will work.

For ur referrence