How to use a parameterized value for comparison in verilog

[arunramnath]

Hello People.

I have a parameter to a module. I have used parameters for but widths and stuff usually. But I am in a different need now.

I am using a FSM which is based on a counter. I am trying to control one of the state changes based on the comparison between count and the value specified by the parameter. To be precise, I am trying to do somthing like this

module xyz #(parameter COUNT_STOP = 3) (....);
...
...
...
assign change_state = (count == COUNT_STOP);
...

I strongly feel we cannot use this as a synthesizable code. So, I want count to be compared to a constant, that depends on the corressponding instantiation. If so, Can someone help me in getting a way to do this ?

Thanks

 

[ads_ee]

module xyz #(parameter COUNT_STOP = 3) (....);
...
...
...
assign change_state = (count == COUNT_STOP);
...
Thanks

It works fine. I use this type of code all over the place. As the parameter is a constant at compile time the value of COUNT_STOP will be synthesizable. I also use it in generate statements to produce compile time variations of a design with more datapaths.

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Code Verilog - [expand]
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module abc #(parameter pNUM_CHAN=4) (...)
...
genrate genvar i
for (i=0;i<pNUM_CHAN;i=i+1) begin : GEN_XYZ
  assign xyz[i] = fgh[i];
end
...
end module

---

 

[arunramnath]

Thanks ads_ee.

In case of generate statement, I think the compiler creates instatantiates/creates logic as asked for. But the parameter pNUM_CHAN is not getting synthesized. Its the bus that is getting created right.

So, based on that, if the Parameter as I have asked for is synthesizable, what will the bitwidth taken for the comparator which checks for equality? With the synthesis tool automatically take it, for example a 2 bit bus for constant 3 ? An explanation on this will help me a lot.

Thanks
Arun

 

[dave_59]

Verilog assumes parameters are 32-bit signed integers unless you supply a different data type or put a size on the value (parameter COUNT_STOP =2'd3 or parameter bit [0:1] COUNT_STOP = 3) .

In this case, it does not matter because the equality will pad count with constant 0's to match the size of COUNT_STOP. The synthesis tool will reduce the comparator to the size of count because padded bits are all being compared to constants.

 

[arunramnath]

Thanks Dave. So I can say the same applies to localparam too.

 

[ads_ee]

same would apply to localparam usage, but will be restricted to the module where the localparam is declared.