how to use 2 "clk" in one "process"!! ??

[vvsvv]

As to What I know, only one clk may used in one process,
however, I have to use 2 clks in process , how to do it!??????

MAY I.....
----------------------------------------------------------------
cnt_pel_Process (CLK2, RESET)
begin
if (vref'event and vref= '1' and rts0= '1') or (reset = '1') then
cnt_pel <= 0;
elsif CLK2='1' and CLK2'event then
if (cnt_pel >= MAX_PEL) then cnt_pel <= 0;
else
cnt_pel <= cnt_pel + 1;
end if;

end if;
end process cnt_pel_p;
----------------------------------------------
Thank you for your advice!!!!!!!!!!

 

[vvsvv]

sorry! I forget to say something:

VREF is another "clk",
its frequency is much more lower than clk2!!

Fvref = 1/(720*576) * Fclk2

 

[alba800]

Re: how to use 2 "clk" in one "process"!

You will have to make two processes, one for each clock value, and then you should set up some mechanism to get them synchronized one to each other

 

[gnomix]

Re: how to use 2 "clk" in one "process"!

As to What I know, only one clk may used in one process,
however, I have to use 2 clks in process , how to do it!??????

MAY I.....
----------------------------------------------------------------
cnt_pel_Process (CLK2, RESET)
begin
if (vref'event and vref= '1' and rts0= '1') or (reset = '1') then
cnt_pel <= 0;
elsif CLK2='1' and CLK2'event then
if (cnt_pel >= MAX_PEL) then cnt_pel <= 0;
else
cnt_pel <= cnt_pel + 1;
end if;

end if;
end process cnt_pel_p;
----------------------------------------------
Thank you for your advice!!!!!!!!!!

You can use only a single clock (CLK2) and re-sample the "vfef" to generate a synchronous reset.
See the following example


....
signal sync_reset : std_logic;
signal vref_sh : std_logic_vector(2 downto 0);
....
....
....
begin

-- generate a one CLK2 pulse width on the rising edge of "vref" after 3 CLK2 period.
process (CLK2, RESET)
begin
if reset='1' then
vref_sh<=(others=>'0');
sync_reset <='0';
elsif clk2'event and clk2='1' then
vref_sh(0) <= vref;
vref_sh(2 downto 1) <= vref_sh(1 downto 0);
if vref_sh(2 downto 1)="01" then
sync_reset<=rts0;
else
sync_reset <='0';
end if;
end if;
end process;


cnt_pel_Process (CLK2, RESET)
begin
if (reset = '1') then
cnt_pel <= 0;
elsif CLK2='1' and CLK2'event then
if (cnt_pel >= MAX_PEL) or sync_reset='1' then
cnt_pel <= 0;
else
cnt_pel <= cnt_pel + 1;
end if;

end if;
end process cnt_pel_p;

 

[vvsvv]

thanks first!
but, does these code produce the condition that
"if (vref'event and vref= '1' and rts0= '1') or (reset = '1') "??

and what's more,
if I do not want 3 clk2' period delay? I just want to prodece one clk period pluse as soon as the condition is meet with "no delay " ? how to do it then?
thanks again!

 

[gnomix]

Re: how to use 2 "clk" in one "process"!

>but, does these code produce the condition that
>"if (vref'event and vref= '1' and rts0= '1') or (reset = '1') "??

The difference is that in my source the"(vref'event and vref= '1' and rts0= '1')" reset is syncronous with the CLK2.
see the attached wave.

>if I do not want 3 clk2' period delay? I just want to prodece one clk period pluse as soon as the condition is meet with "no delay " ? how to do it then?
>thanks again!

You can reduce the delay (ses the following code) but attention to metastability problems.


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Prova IS
PORT
(
CLK2, RESET,vref,rts0 : IN STD_LOGIC ;
cnt_pel : buffer integer range 0 to 15
);
END prova;
ARCHITECTURE SYN OF prova IS
signal vref_sh : std_logic;
constant MAX_PEL : integer:=14;
begin
process (CLK2, RESET)
begin
if reset='1' then
vref_sh<='0';
elsif clk2'event and clk2='1' then
vref_sh <= vref;
end if;
end process;

cnt_pel_Process (CLK2, RESET)
begin
if (reset = '1') then
cnt_pel <= 0;
elsif CLK2='1' and CLK2'event then
if (cnt_pel >= MAX_PEL) or (vref_sh='0' and vref='1' and rts0='1' ) then
cnt_pel <= 0;
else
cnt_pel <= cnt_pel + 1;
end if;
end if;
end process cnt_pel_p;
end SYN;

 

[roger]

Re: how to use 2 "clk" in one "process"!

since HDL means hardware description language,
so you got to think does it exist any flip-flop cell with two
clk driving? if not, how come you need two clk in a process?
I doubt?