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How to update output port in two process

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mpatel

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I want to detect input signal at both edges of clock. I wrote following code but in synthesis it shows the error "signal is driven by multiple primitives".

ENTITY clk_event IS
port(
clk : in std_ulogic;
din : in std_logic;
dout : out std_logic
);
END ENTITY clk_event;

--
ARCHITECTURE clk_event OF clk_event IS
signal temp : std_logic;
BEGIN

rise:process
begin
if rising_edge(clk)then
temp <= din;
end if;
end process;

fall:process
begin
if falling_edge(clk)then
temp <= din;
end if;
end process;

dout <= temp;

END ARCHITECTURE clk_event;

Is there any way to overcome this problem?
 

what processor? Can you use interrupt and set the capture sense both up jump and down jump?
 

ENTITY clk_event IS
port(
clk : in std_ulogic;
din : in std_logic;
dout : out std_logic
);
END ENTITY clk_event;

--
ARCHITECTURE clk_event OF clk_event IS
signal temp : std_logic;
BEGIN

rise:process
begin
if (clk'event) then
temp <= din;
end if;
end process;

dout <= temp;

END ARCHITECTURE clk_event;
 

1). you cannot update any signal in 2 different processes.
2). the solution suggested by master_picengineer may work, but then it is not synthesizeable. you cannot have a flop which works on both +ive and -ive edge.
your solution will be capture your signal in two signals temp1 and temp2 in two different processes, one driven by rising_edge(clk) and the other driven by falling_edge(clk).
Then you may have
dout <= temp1 Or temp2.
hope it helps,
kr,
avi
http://www.vlsiip.com
 

avimit said:
your solution will be capture your signal in two signals temp1 and temp2 in two different processes, one driven by rising_edge(clk) and the other driven by falling_edge(clk).
Then you may have
dout <= temp1 Or temp2.
http://www.vlsiip.com
Click to expand...

Hi Avi,

Please avi, could you explain your solution. In fact I analysed it and I don't see how this solution can resolve the problem.
Let suppose Din=1.
at the first rising edge Dout<=1 since (temp1=1). Now suppose that after that Din resets, so at the falling edge we should have Din=0 (temps2=0). Thats not true since temps1=1 and Dout= temp1 Or temp2=1.

Even If you suggest to reset temps1 and temps2 at each clk'event we'll have the errors. "unresolved signal" guiven that process 1 has to reset temps2 and process2 has to reset temps1.

Thanks in advance.
 

Well, master_picengineer,
It depends why you want to clock the signal on both edges. There is no singble flipflop which can do that for you. So you will have to capture them in two different flops, one working on +ive edge and the other on -ive edge.
Then you can make use of the o/s from these two, as I have suggested. I have Ord them, thinking a possible use of it. But yes, you can use them as two signals, and do whatever you want to do with them.
But you CANNOT have
1). A signal updated in two different processes
2). A flop working on both edges.
Kr,
Avi
http://www.vlsiip.com
 

Hi all,

I think the only way to acheive this requirement in a clean manner is to use a higher frequency clock (double) synchronized with the original clock.

Correct me if I'm mistaken.

Yours,
Said.
 

Thanks avimit,

I know a book:
A Practical Guide to VHDL Design
it's discuss the pros of double-edge clocking

I'm looking for this book for a long time and I couldn't find it.
Please who have it upload.

Thanks in advance.
 

shnain said:
Hi all,

I think the only way to acheive this requirement in a clean manner is to use a higher frequency clock (double) synchronized with the original clock.

Correct me if I'm mistaken.

Yours,
Said.
Click to expand...

Hey shnain,

Can you please explain me how to double the clock in VHDL code.

thanks

Added after 3 minutes:

master_picengineer said:
Thanks avimit,

I know a book:
A Practical Guide to VHDL Design
it's discuss the pros of double-edge clocking

I'm looking for this book for a long time and I couldn't find it.
Please who have it upload.

Thanks in advance.
Click to expand...

Hi master_picengineer,

Can you give me the full details about the book

e.g. full name, author's name, publication, ISBN number if available

I shall search on the internet and also post you if you want.

thanks
 

You won't synthesize properly in two processes.
 

Can you give me the full details about the book

e.g. full name, author's name, publication, ISBN number if available

I shall search on the internet and also post you if you want.

thanks
Click to expand...

**broken link removed**

it's the book mentioned here....
if you find it please tell us all :D

thanks in advance,
Salma
 

Hi,

Here are the details

A Practical Guide to VHDL Design

M. Cirstea, A. Dinu, D. Nicula
Editura Tehnica, Bucharest, Romania
ISBN: 973-31-1539-8

If you need anything else please let me know...
and if you get it of course, the whole thread wants it :)

thanks in advance
 

salma ali bakr said:
Hi,

Here are the details

A Practical Guide to VHDL Design

M. Cirstea, A. Dinu, D. Nicula
Editura Tehnica, Bucharest, Romania
ISBN: 973-31-1539-8

If you need anything else please let me know...
and if you get it of course, the whole thread wants it :)

thanks in advance
Click to expand...

Thanks Salma,

At this moment I could not download that book. But I have found almost similar book.

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
John Wiley & Sons, 2006

I would upload this tomorrow, hope it may work but I will keep searching for other book.
 

mpatel said:
Hey shnain,

Can you please explain me how to double the clock in VHDL code.

thanks
Click to expand...

Hi,

I know that their is no way to multiply clock in VHDL we can only divide.

What I meant by using a double clock is to have it from PLL.

Yours,
Said.
 

Hi,

Won't the modified code of master_picengineer below work...??

Code: 
ENTITY clk_event IS 
.......
.......

rise:process 
begin 
if (clk'event and (clk = '1' or clk = '0')) then 
temp <= din; 
end if; 
end process; 

dout <= temp; 

END ARCHITECTURE clk_event;

-mkrishnap
 

Hi,

This can work in simulation you can keep only :

Code: 
    if clk'event then
    ...

but coming to synthesis you will not be able to find a clock working on both edges!!

from a system view the architect should know about those limitations and define protocols to run preferably on one edge. (falling edge usage is generally avoided for better testability but a work around is possible if the falling edge is inevitable)
and also define the clock frequency that fit the best with the requirements.

Yours.
 

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