mpatel
Member level 4
I want to detect input signal at both edges of clock. I wrote following code but in synthesis it shows the error "signal is driven by multiple primitives".
ENTITY clk_event IS
port(
clk : in std_ulogic;
din : in std_logic;
dout : out std_logic
);
END ENTITY clk_event;
--
ARCHITECTURE clk_event OF clk_event IS
signal temp : std_logic;
BEGIN
riserocess
begin
if rising_edge(clk)then
temp <= din;
end if;
end process;
fallrocess
begin
if falling_edge(clk)then
temp <= din;
end if;
end process;
dout <= temp;
END ARCHITECTURE clk_event;
Is there any way to overcome this problem?
ENTITY clk_event IS
port(
clk : in std_ulogic;
din : in std_logic;
dout : out std_logic
);
END ENTITY clk_event;
--
ARCHITECTURE clk_event OF clk_event IS
signal temp : std_logic;
BEGIN
riserocess
begin
if rising_edge(clk)then
temp <= din;
end if;
end process;
fallrocess
begin
if falling_edge(clk)then
temp <= din;
end if;
end process;
dout <= temp;
END ARCHITECTURE clk_event;
Is there any way to overcome this problem?