avimit said:your solution will be capture your signal in two signals temp1 and temp2 in two different processes, one driven by rising_edge(clk) and the other driven by falling_edge(clk).
Then you may have
dout <= temp1 Or temp2.
http://www.vlsiip.com
shnain said:Hi all,
I think the only way to acheive this requirement in a clean manner is to use a higher frequency clock (double) synchronized with the original clock.
Correct me if I'm mistaken.
Yours,
Said.
master_picengineer said:Thanks avimit,
I know a book:
A Practical Guide to VHDL Design
it's discuss the pros of double-edge clocking
I'm looking for this book for a long time and I couldn't find it.
Please who have it upload.
Thanks in advance.
Can you give me the full details about the book
e.g. full name, author's name, publication, ISBN number if available
I shall search on the internet and also post you if you want.
thanks
salma ali bakr said:Hi,
Here are the details
A Practical Guide to VHDL Design
M. Cirstea, A. Dinu, D. Nicula
Editura Tehnica, Bucharest, Romania
ISBN: 973-31-1539-8
If you need anything else please let me know...
and if you get it of course, the whole thread wants it
thanks in advance
mpatel said:Hey shnain,
Can you please explain me how to double the clock in VHDL code.
thanks
ENTITY clk_event IS
.......
.......
rise:process
begin
if (clk'event and (clk = '1' or clk = '0')) then
temp <= din;
end if;
end process;
dout <= temp;
END ARCHITECTURE clk_event;
if clk'event then
...
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