joe_chuang
Newbie level 6

Does any one know how to translate Verilog (GATE Level) to Spice(with Standard Cell)?
Thanks.
Thanks.
Nobody said:May u can try the ECS (Cohesion ).
They have ASCII library format.
And there are SDK which can build ur own script to solve ur problem by programing their tool.
I saw there is a sample script to translate
verilog into symbol lib.