prakashvenugopal
Advanced Member level 1
Hi,
How to translate this verilog code to vhdl code. Please do let me know.
Thanks,
V. Prakash
How to translate this verilog code to vhdl code. Please do let me know.
reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse
always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;
// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);
Thanks,
V. Prakash