reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse
always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;
// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);
--DVAL:
reg dval = 1; // dval output to external video data sources, roughly 301.82KHz (3.31325uS)
always @(posedge clk16M6) dval <= (counter < 28); // dval has 28/27 duty cycle
--LVAL:
reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;
always @(posedge clk16M6)
if (enable1u66)
case(lvalstate)
0: // Keep LVAL low for 44 cycles
if (lvalcount == 43) begin // LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;
1: // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin // HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;
endcase