Okay ThisIsNotSam, that's what I do for know. The problem I had is with the leaf cells generated from the assign statements and muxes and stuff like that.
I'm working this around by isolating each part in a separate module in order for its consumption to be visible in the PrimeTime Power hierarchical reports.
Thanks fo the information anyway!
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Do you if there are any way to label particular statements (for example assign) in SystemVerilog? Or any other way to generate an additional hierarchy level other than using modules would do the trick.
I tried for example dummy generate like the following, but obviously it gets optimized away by DC.
Code:
genvar i;
generate
for (i = 0; i < 1; i++) begin : label
assign output = Some_Logic_Op_Here ;
end
endgenerate
[\CODE][/QUOTE]
this analysis is so fine grained, it's hard to think why one owuld need to understand the power consumption of a handful of cells when a modern IP has 1M+ cells.