No doubt, how well ESD can be avoided is depends on the protection circuits. However, layout play important role also.
What i normally do is to minimize ESD path resistance to < 0.5Ohm at any possible cases, by using wide metal and stacked metal. You can use a typical HBM model to simulate the ESD circuit + manually add some reasonable metal resistance based on your final layout. This could better tells how well your ESD protection is before tapeout.
Pls tell me if there is any other clever method using Cadence. Thanks.